Aerial CUDA-Accelerated RAN 24-2.1

Aerial CUDA-Accelerated RAN 24-2.1 Download PDF

Aerial CUDA-Accelerated RAN brings together the Aerial software for 5G and AI frameworks and the NVIDIA accelerated computing platform, enabling TCO reduction and unlocking infrastructure monetization for telcos.

Aerial CUDA-Accelerated RAN has the following key features:

  • Software-defined, scalable, modular, highly programmable and cloud-native, without any fixed function accelerators. Enables the ecosystem to flexibly adopt necessary modules for their commercial products.

  • Full-stack acceleration of DU L1, DU L2+, CU, UPF and other network functions, enabling workload consolidation for maximum performance and spectral efficiency, leading to best-in-class system TCO.

  • General purpose infrastructure, with multi-tenancy that can power both traditional workloads and cutting-edge AI applications for best-in-class RoA.

What’s New in 24-2.1

The following new features are available in release 24-2.1 for Aerial CUDA-Accelerated RAN:

  • Aerial cuPHY: CUDA accelerated inline PHY

    • 64T64R Massive MIMO:

      • 100 MHz DL max combined 16 layers + UL max combined 8 layers + SRS

      • 64T64R SRS + Dynamic + Static Beamforming Weights

      • Support multiple dynamic UE groups

      • Support flexible PRG size and PRB number

      • Support SRS buffer indexing from L2

      • Support non 2^n layers

      • Use different section IDs when splitting the C-Plane section

      • FH messaging for CSIRS + PDSCH and other channel combinations

    • Support GH200+BF3 as RU emulator platform

What’s New in 24-2

The following new features are available in release 24-2 for Aerial CUDA-Accelerated RAN:

  • Aerial cuPHY: CUDA accelerated inline PHY

    • MGX Grace Hopper multicell capacity w/ telco-grade traffic model

      • 20 peak loaded 4T4R @ 100MHz

      • Capacity also validated with more challenging traffic model

        • PUSCH and PDCCH symbols in the S-slot

    • L1-L2 interface enhancements

      • Separate FAPI request timelines for PDSCH and PDCCH

  • Aerial cuMAC: CUDA accelerated MAC scheduler

    • cuMAC-Sch

      • 4T4R CUDA implementation complete

    • cuMAC-CP

      • 4T4R implementation (Functional – early access)

  • Aerial cuBB/E2E: System level / End-to-End validation

    • Over-The-Air (OTA) validation:

      • CBRS O-RU

      • 8 UE OTA w/ 6 UE/TTI for > 8 hours

    • RedHat-OCP:

      • Multicell capacity validated on MGX (GH200+BF3)

    • O-RAN Fronthaul:

      • 16-bit fixed point IQ sample validated E2E (Keysight eLSU)

      • Simultaneous dual-port FH capability (8 peak cells; 4 per port)

    • L2 integration:

      • Multi-L2 container instances per L1 validated E2E

  • pyAerial: Python interface to Aerial cuPHY

    • TensorRT inference engine

      • Jupyter notebook example using pyAerial to validate a neural PUSCH receiver

    • LDPC API improvements

      • Added soft outputs to LDPC decoder

    • LS channel estimation

    • Limited support for Grace Hopper

      • Run pyAerial together with Aerial Data Lakes

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