Tuning CUDA Applications for NVIDIA Ada GPU Architecture
The programming guide for tuning CUDA Applications for GPUs based on the NVIDIA Ada GPU Architecture.
1. NVIDIA Ada GPU Architecture Tuning Guide
1.1. NVIDIA Ada GPU Architecture
The NVIDIA® Ada GPU architecture is NVIDIA’s latest architecture for CUDA® compute applications. The NVIDIA Ada GPU architecture retains and extends the same CUDA programming model provided by previous NVIDIA GPU architectures such as NVIDIA Ampere and Turing, and applications that follow the best practices for those architectures should typically see speedups on the NVIDIA Ada architecture without any code changes. This guide summarizes the ways that an application can be fine-tuned to gain additional speedups by leveraging the NVIDIA Ada GPU architecture’s features.1
For further details on the programming features discussed in this guide, please refer to the CUDA C++ Programming Guide.
1.2. CUDA Best Practices
The performance guidelines and best practices described in the CUDA C++ Programming Guide and the CUDA C++ Best Practices Guide apply to all CUDA-capable GPU architectures. Programmers must primarily focus on following those recommendations to achieve the best performance.
The high-priority recommendations from those guides are as follows:
Find ways to parallelize sequential code.
Minimize data transfers between the host and the device.
Adjust kernel launch configuration to maximize device utilization.
Ensure global memory accesses are coalesced.
Minimize redundant accesses to global memory whenever possible.
Avoid long sequences of diverged execution by threads within the same warp.
1.3. Application Compatibility
Before addressing specific performance tuning issues covered in this guide, refer to the NVIDIA Ada GPU Architecture Compatibility Guide for CUDA Applications to ensure that your application is compiled in a way that is compatible with the NVIDIA Ada GPU Architecture.
1.4. NVIDIA Ada GPU Architecture Tuning
1.4.1. Streaming Multiprocessor
The NVIDIA Ada GPU architecture’s Streaming Multiprocessor (SM) provides the following improvements over Turing and NVIDIA Ampere GPU architectures.
The maximum number of concurrent warps per SM is 48, remaining the same compared to compute capability 8.6 GPUs, and other factors influencing warp occupancy are:
The register file size is 64K 32-bit registers per SM.
The maximum number of registers per thread is 255.
The maximum number of thread blocks per SM is 24.
The shared memory capacity per SM is 100 KB.
The maximum shared memory per thread block is 99 KB.
Overall, developers can expect similar occupancy as on compute capability 8.6 GPUs without changes to their application.
126.96.36.199. Improved Tensor Core Operations
The NVIDIA Ada GPU architecture includes new Ada Fourth Generation Tensor Cores featuring the Hopper FP8 Transformer Engine.
188.8.131.52. Improved FP32 throughput
Devices of compute capability 8.9 have 2x more FP32 operations per cycle per SM than devices of compute capability 8.0. While a binary compiled for 8.0 will run as-is on 8.9, it is recommended to compile explicitly for 8.9 to benefit from the increased FP32 throughput.
1.4.2. Memory System
184.108.40.206. Increased L2 capacity
The NVIDIA Ada GPU architecture increases the capacity of the L2 cache to 98304 KB in AD102, 16x larger than GA102. The NVIDIA Ada GPU architecture allows CUDA users to control the persistence of data in the L2 cache. For more information on the persistence of data in the L2 cache, refer to the section on managing the L2 cache in the CUDA C++ Programming Guide.
2. Revision History
Initial Public Release
Added support for compute capability 8.9
Throughout this guide, Volta refers to devices of compute capability 7.0, Turing refers to devices of compute capability 7.5, NVIDIA Ampere GPU Architecture refers to devices of compute capability 8.0 and 8.6, NVIDIA Ada refers to devices of compute capability 8.9.
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