NVIDIA Performance Primitives (NPP)  Version 9.1
nppdefs.h
1  /* Copyright 2009-2016 NVIDIA Corporation. All rights reserved.
2  *
3  * NOTICE TO LICENSEE:
4  *
5  * The source code and/or documentation ("Licensed Deliverables") are
6  * subject to NVIDIA intellectual property rights under U.S. and
7  * international Copyright laws.
8  *
9  * The Licensed Deliverables contained herein are PROPRIETARY and
10  * CONFIDENTIAL to NVIDIA and are being provided under the terms and
11  * conditions of a form of NVIDIA software license agreement by and
12  * between NVIDIA and Licensee ("License Agreement") or electronically
13  * accepted by Licensee. Notwithstanding any terms or conditions to
14  * the contrary in the License Agreement, reproduction or disclosure
15  * of the Licensed Deliverables to any third party without the express
16  * written consent of NVIDIA is prohibited.
17  *
18  * NOTWITHSTANDING ANY TERMS OR CONDITIONS TO THE CONTRARY IN THE
19  * LICENSE AGREEMENT, NVIDIA MAKES NO REPRESENTATION ABOUT THE
20  * SUITABILITY OF THESE LICENSED DELIVERABLES FOR ANY PURPOSE. THEY ARE
21  * PROVIDED "AS IS" WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.
22  * NVIDIA DISCLAIMS ALL WARRANTIES WITH REGARD TO THESE LICENSED
23  * DELIVERABLES, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
24  * NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE.
25  * NOTWITHSTANDING ANY TERMS OR CONDITIONS TO THE CONTRARY IN THE
26  * LICENSE AGREEMENT, IN NO EVENT SHALL NVIDIA BE LIABLE FOR ANY
27  * SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, OR ANY
28  * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
29  * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS
30  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
31  * OF THESE LICENSED DELIVERABLES.
32  *
33  * U.S. Government End Users. These Licensed Deliverables are a
34  * "commercial item" as that term is defined at 48 C.F.R. 2.101 (OCT
35  * 1995), consisting of "commercial computer software" and "commercial
36  * computer software documentation" as such terms are used in 48
37  * C.F.R. 12.212 (SEPT 1995) and are provided to the U.S. Government
38  * only as a commercial end item. Consistent with 48 C.F.R.12.212 and
39  * 48 C.F.R. 227.7202-1 through 227.7202-4 (JUNE 1995), all
40  * U.S. Government End Users acquire the Licensed Deliverables with
41  * only those rights set forth herein.
42  *
43  * Any use of the Licensed Deliverables in individual and commercial
44  * software must include, in the user documentation and internal
45  * comments to the code, the above Disclaimer and U.S. Government End
46  * Users Notice.
47  */
48 #ifndef NV_NPPIDEFS_H
49 #define NV_NPPIDEFS_H
50 
51 #include <stdlib.h>
52 #include <host_defines.h>
53 
60 #ifdef __cplusplus
61 extern "C" {
62 #endif
63 
64  // If this is a 32-bit Windows compile, don't align to 16-byte at all
65  // and use a "union-trick" to create 8-byte alignment.
66 #if defined(_WIN32) && !defined(_WIN64)
67 
68  // On 32-bit Windows platforms, do not force 8-byte alignment.
69  // This is a consequence of a limitation of that platform.
70  #define NPP_ALIGN_8
71  // On 32-bit Windows platforms, do not force 16-byte alignment.
72  // This is a consequence of a limitation of that platform.
73  #define NPP_ALIGN_16
74 
75 #else /* _WIN32 && !_WIN64 */
76 
77  #define NPP_ALIGN_8 __align__(8)
78  #define NPP_ALIGN_16 __align__(16)
79 
80 #endif /* !__CUDACC__ && _WIN32 && !_WIN64 */
81 
82 
90 typedef enum
91 {
102  NPPI_SMOOTH_EDGE = (1 << 31)
104 
108 typedef enum
109 {
115 
119 typedef enum
120 {
123  NPP_MASK_SIZE_3_X_1 = 100, // leaving space for more 1 X N type enum values
125  NPP_MASK_SIZE_3_X_3 = 200, // leaving space for more N X 1 type enum values
132 } NppiMaskSize;
133 
138 typedef enum
139 {
143 
152 typedef enum
153 {
154  /* negative return-codes indicate errors */
156 
170 
220  NPP_ERROR = -2,
222 
223  /* success */
227  /* positive return-codes indicate warnings */
237 } NppStatus;
238 
239 typedef enum
240 {
243  NPP_CUDA_1_0 = 100,
244  NPP_CUDA_1_1 = 110,
245  NPP_CUDA_1_2 = 120,
246  NPP_CUDA_1_3 = 130,
247  NPP_CUDA_2_0 = 200,
248  NPP_CUDA_2_1 = 210,
249  NPP_CUDA_3_0 = 300,
250  NPP_CUDA_3_2 = 320,
251  NPP_CUDA_3_5 = 350,
252  NPP_CUDA_3_7 = 370,
253  NPP_CUDA_5_0 = 500,
254  NPP_CUDA_5_2 = 520,
255  NPP_CUDA_5_3 = 530,
256  NPP_CUDA_6_0 = 600,
257  NPP_CUDA_6_1 = 610,
258  NPP_CUDA_6_2 = 620,
259  NPP_CUDA_6_3 = 630,
262 
263 typedef struct
264 {
265  int major;
266  int minor;
267  int build;
269 
275 typedef unsigned char Npp8u;
276 typedef signed char Npp8s;
277 typedef unsigned short Npp16u;
278 typedef short Npp16s;
279 typedef unsigned int Npp32u;
280 typedef int Npp32s;
281 typedef unsigned long long Npp64u;
282 typedef long long Npp64s;
283 typedef float Npp32f;
284 typedef double Npp64f;
291 typedef struct __align__(2)
292 {
293  Npp8u re;
294  Npp8u im;
296 
301 typedef struct __align__(4)
302 {
303  Npp16u re;
304  Npp16u im;
306 
311 typedef struct __align__(4)
312 {
313  Npp16s re;
314  Npp16s im;
316 
321 typedef struct NPP_ALIGN_8
322 {
323  Npp32u re;
324  Npp32u im;
325 } Npp32uc;
326 
331 typedef struct NPP_ALIGN_8
332 {
333  Npp32s re;
334  Npp32s im;
335 } Npp32sc;
336 
341 typedef struct NPP_ALIGN_8
342 {
343  Npp32f re;
344  Npp32f im;
345 } Npp32fc;
346 
351 typedef struct NPP_ALIGN_16
352 {
353  Npp64s re;
354  Npp64s im;
355 } Npp64sc;
356 
361 typedef struct NPP_ALIGN_16
362 {
363  Npp64f re;
364  Npp64f im;
365 } Npp64fc;
366 
369 #define NPP_MIN_8U ( 0 )
370 #define NPP_MAX_8U ( 255 )
371 #define NPP_MIN_16U ( 0 )
372 #define NPP_MAX_16U ( 65535 )
373 #define NPP_MIN_32U ( 0 )
374 #define NPP_MAX_32U ( 4294967295U )
375 #define NPP_MIN_64U ( 0 )
376 #define NPP_MAX_64U ( 18446744073709551615ULL )
378 #define NPP_MIN_8S (-127 - 1 )
379 #define NPP_MAX_8S ( 127 )
380 #define NPP_MIN_16S (-32767 - 1 )
381 #define NPP_MAX_16S ( 32767 )
382 #define NPP_MIN_32S (-2147483647 - 1 )
383 #define NPP_MAX_32S ( 2147483647 )
384 #define NPP_MAX_64S ( 9223372036854775807LL )
385 #define NPP_MIN_64S (-9223372036854775807LL - 1)
387 #define NPP_MINABS_32F ( 1.175494351e-38f )
388 #define NPP_MAXABS_32F ( 3.402823466e+38f )
389 #define NPP_MINABS_64F ( 2.2250738585072014e-308 )
390 #define NPP_MAXABS_64F ( 1.7976931348623158e+308 )
396 typedef struct
397 {
398  int x;
399  int y;
400 } NppiPoint;
401 
405 typedef struct {
406  Npp32f rho;
407  Npp32f theta;
408 } NppPointPolar;
409 
415 typedef struct
416 {
417  int width;
418  int height;
419 } NppiSize;
420 
428 typedef struct
429 {
430  int x;
431  int y;
432  int width;
433  int height;
434 } NppiRect;
435 
436 typedef enum
437 {
441 } NppiAxis;
442 
443 typedef enum
444 {
450 } NppCmpOp;
451 
465 typedef enum
466 {
479 
490 
500 
501  /*
502  * Other rounding modes supported by IEEE-754 (2008) floating-point standard:
503  *
504  * - NPP_ROUND_TOWARD_INFINITY // ceiling
505  * - NPP_ROUND_TOWARD_NEGATIVE_INFINITY // floor
506  *
507  */
508 } NppRoundMode;
509 
510 typedef enum
511 {
519 
520 
521 typedef enum {
526 
527 /*
528  * Alpha composition controls.
529  */
530 
531 typedef enum {
545 } NppiAlphaOp;
546 
547 
552 typedef struct
553 {
554  int cellSize;
558 } NppiHOGConfig;
559 
560 #define NPP_HOG_MAX_CELL_SIZE (16)
561 #define NPP_HOG_MAX_BLOCK_SIZE (64)
562 #define NPP_HOG_MAX_BINS_PER_CELL (16)
563 #define NPP_HOG_MAX_CELLS_PER_DESCRIPTOR (256)
564 #define NPP_HOG_MAX_OVERLAPPING_BLOCKS_PER_DESCRIPTOR (256)
565 #define NPP_HOG_MAX_DESCRIPTOR_LOCATIONS_PER_CALL (128)
567 typedef struct
568 {
570  Npp32s * classifiers;
573  Npp32s * counterDevice;
575 
576 typedef struct
577 {
579  Npp32s * haarBuffer;
582 
583 typedef enum {
587 } NppsZCType;
588 
589 typedef enum {
593 
594 typedef enum {
598 } NppiNorm;
599 
600 
601 #ifdef __cplusplus
602 } /* extern "C" */
603 #endif
604 
607 #endif /* NV_NPPIDEFS_H */
NppGpuComputeCapability
Definition: nppdefs.h:239
Definition: nppdefs.h:447
Definition: nppdefs.h:540
Definition: nppdefs.h:204
Definition: nppdefs.h:210
Definition: nppdefs.h:162
Speed reduction due to uncoalesced memory accesses warning.
Definition: nppdefs.h:235
Channel of interest is not 1, 2, or 3.
Definition: nppdefs.h:190
NppiMaskSize
Fixed filter-kernel sizes.
Definition: nppdefs.h:119
Indicates that CUDA 7.0 or better is machine&#39;s default device.
Definition: nppdefs.h:260
Npp32f re
Real part.
Definition: nppdefs.h:343
Indicates that CUDA 6.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:257
Image pixels are constant for quality index.
Definition: nppdefs.h:173
Definition: nppdefs.h:517
Definition: nppdefs.h:131
Npp32u im
Imaginary part.
Definition: nppdefs.h:324
struct NPP_ALIGN_8 Npp32uc
Complex Number This struct represents an unsigned int complex number.
int height
Rectangle height.
Definition: nppdefs.h:418
Round to the nearest even integer.
Definition: nppdefs.h:477
Definition: nppdefs.h:128
int haarBufferSize
size of the buffer
Definition: nppdefs.h:578
Definition: nppdefs.h:439
Indicates that CUDA 1.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:245
unsigned char Npp8u
8-bit unsigned chars
Definition: nppdefs.h:275
Definition: nppdefs.h:122
Definition: nppdefs.h:163
Definition: nppdefs.h:217
Definition: nppdefs.h:212
Definition: nppdefs.h:169
struct __align__(2)
Complex Number This struct represents an unsigned char complex number.
Definition: nppdefs.h:291
Complex Number This struct represents an unsigned int complex number.
Definition: nppdefs.h:321
Definition: nppdefs.h:516
int y
y-coordinate of upper left corner (lowest memory address).
Definition: nppdefs.h:431
sum
Definition: nppdefs.h:596
Npp64f re
Real part.
Definition: nppdefs.h:363
Definition: nppdefs.h:167
Definition: nppdefs.h:126
Definition: nppdefs.h:127
Indicates that CUDA 5.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:254
Definition: nppdefs.h:523
int y
y-coordinate.
Definition: nppdefs.h:399
Indicates that CUDA 1.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:244
NppiAxis
Definition: nppdefs.h:436
Definition: nppdefs.h:221
Definition: nppdefs.h:161
Definition: nppdefs.h:166
Definition: nppdefs.h:201
The given ROI has no interestion with either the source or destination ROI.
Definition: nppdefs.h:231
NppiBayerGridPosition
Bayer Grid Position Registration.
Definition: nppdefs.h:108
Npp64s re
Real part.
Definition: nppdefs.h:353
NppiSize detectionWindowSize
detection window size (pixels).
Definition: nppdefs.h:557
Definition: nppdefs.h:168
sign change XOR
Definition: nppdefs.h:585
AC Table.
Definition: nppdefs.h:591
NppStatus
Error Status Codes.
Definition: nppdefs.h:152
Definition: nppdefs.h:209
Bad or unsupported number of channels.
Definition: nppdefs.h:189
Npp8uc
Definition: nppdefs.h:295
Image size isn&#39;t multiple of two.
Definition: nppdefs.h:233
Definition: nppdefs.h:440
Definition: nppdefs.h:542
Definition: nppdefs.h:576
Indicates that CUDA 6.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:258
Npp32f theta
Definition: nppdefs.h:407
Definition: nppdefs.h:92
Definition: nppdefs.h:543
Npp32u re
Real part.
Definition: nppdefs.h:323
Wrong order of the destination channels.
Definition: nppdefs.h:183
Complex Number This struct represents a long long complex number.
Definition: nppdefs.h:351
Npp32s * haarBuffer
buffer
Definition: nppdefs.h:579
Indicates that CUDA 3.5 capable device is machine&#39;s default device.
Definition: nppdefs.h:251
sign change count_0
Definition: nppdefs.h:586
Definition: nppdefs.h:438
Npp64s im
Imaginary part.
Definition: nppdefs.h:354
Npp32s re
Real part.
Definition: nppdefs.h:333
Definition: nppdefs.h:215
Step value is not pixel multiple.
Definition: nppdefs.h:178
Linear interpolation.
Definition: nppdefs.h:94
2D Size This struct typically represents the size of a a rectangular region in two space...
Definition: nppdefs.h:415
NppCmpOp
Definition: nppdefs.h:443
Definition: nppdefs.h:522
Definition: nppdefs.h:121
Npp64f im
Imaginary part.
Definition: nppdefs.h:364
Definition: nppdefs.h:203
Definition: nppdefs.h:512
Definition: nppdefs.h:541
Round towards zero (truncation).
Definition: nppdefs.h:498
square root of sum of squares
Definition: nppdefs.h:597
Size of the rectangle region is less than or equal to 1.
Definition: nppdefs.h:186
Definition: nppdefs.h:533
Processed data is corrupted.
Definition: nppdefs.h:182
int x
x-coordinate.
Definition: nppdefs.h:398
Definition: nppdefs.h:445
Indicates that CUDA 5.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:253
Definition: nppdefs.h:218
Definition: nppdefs.h:125
struct NPP_ALIGN_16 Npp64sc
Complex Number This struct represents a long long complex number.
Number of levels for LUT is less than 2.
Definition: nppdefs.h:180
int width
Rectangle width.
Definition: nppdefs.h:417
int build
Build number.
Definition: nppdefs.h:267
int x
x-coordinate of upper left corner (lowest memory address).
Definition: nppdefs.h:430
Definition: nppdefs.h:513
Definition: nppdefs.h:124
Definition: nppdefs.h:515
Definition: nppdefs.h:216
struct NPP_ALIGN_16 Npp64fc
Complex Number This struct represents a double floating-point complex number.
struct NPP_ALIGN_8 Npp32sc
Complex Number This struct represents a signed int complex number.
Indicates that CUDA 2.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:248
long long Npp64s
64-bit signed integers
Definition: nppdefs.h:282
Definition: nppdefs.h:536
int cellSize
square cell size (pixels).
Definition: nppdefs.h:554
Definition: nppdefs.h:200
Definition: nppdefs.h:202
int major
Major version number.
Definition: nppdefs.h:265
Definition: nppdefs.h:539
int Npp32s
32-bit signed integers
Definition: nppdefs.h:280
sign change
Definition: nppdefs.h:584
Definition: nppdefs.h:544
Definition: nppdefs.h:524
Lower bound is larger than upper bound.
Definition: nppdefs.h:197
int minor
Minor version number.
Definition: nppdefs.h:266
NppiInterpolationMode
Filtering methods.
Definition: nppdefs.h:90
Divisor is zero however does not terminate the execution.
Definition: nppdefs.h:229
Round according to financial rule.
Definition: nppdefs.h:488
The given quadrangle has no intersection with either the source or destination ROI.
Definition: nppdefs.h:232
Unallowable values of the transformation coefficients.
Definition: nppdefs.h:187
Alias name for NPP_RND_ZERO.
Definition: nppdefs.h:499
Definition: nppdefs.h:214
2D Rectangle This struct contains position and size information of a rectangle in two space...
Definition: nppdefs.h:428
DC Table.
Definition: nppdefs.h:590
NppiSize classifierSize
Definition: nppdefs.h:572
Error free operation.
Definition: nppdefs.h:224
Indicates that no CUDA capable device was found.
Definition: nppdefs.h:242
Npp16uc
Definition: nppdefs.h:305
Super sampling.
Definition: nppdefs.h:99
Stride is less than the row length.
Definition: nppdefs.h:194
int width
Rectangle width.
Definition: nppdefs.h:432
Definition: nppdefs.h:213
Npp16sc
Definition: nppdefs.h:315
Indicates that CUDA 3.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:249
Number overflows the upper or lower limit of the data type.
Definition: nppdefs.h:177
unsigned short Npp16u
16-bit unsigned integers
Definition: nppdefs.h:277
NppiNorm
Definition: nppdefs.h:594
Indicates that CUDA 1.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:246
Alias name for NPP_RND_NEAR.
Definition: nppdefs.h:478
NppRoundMode
Rounding Modes.
Definition: nppdefs.h:465
size_t classifierStep
Definition: nppdefs.h:571
Indicates that the compute-capability query failed.
Definition: nppdefs.h:241
Definition: nppdefs.h:534
Npp32s * counterDevice
Definition: nppdefs.h:573
int histogramBlockSize
square histogram block size (pixels).
Definition: nppdefs.h:555
Indicates that CUDA 3.7 capable device is machine&#39;s default device.
Definition: nppdefs.h:252
Indicates that CUDA 6.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:259
Definition: nppdefs.h:158
Npp32s * classifiers
packed classifier data 40 bytes each
Definition: nppdefs.h:570
Definition: nppdefs.h:535
Definition: nppdefs.h:207
Definition: nppdefs.h:532
Definition: nppdefs.h:112
NppiHuffmanTableType
Definition: nppdefs.h:589
short Npp16s
16-bit signed integers
Definition: nppdefs.h:278
Definition: nppdefs.h:111
unsigned int Npp32u
32-bit unsigned integers
Definition: nppdefs.h:279
Anchor point is outside mask.
Definition: nppdefs.h:196
Definition: nppdefs.h:205
signed char Npp8s
8-bit signed chars
Definition: nppdefs.h:276
Definition: nppdefs.h:206
unsigned long long Npp64u
64-bit unsigned integers
Definition: nppdefs.h:281
Nearest neighbor filtering.
Definition: nppdefs.h:93
Definition: nppdefs.h:130
Smooth edge filtering.
Definition: nppdefs.h:102
Alias name for NPP_RND_FINANCIAL.
Definition: nppdefs.h:489
Illegal channel index.
Definition: nppdefs.h:193
Default registration position.
Definition: nppdefs.h:110
double Npp64f
64-bit floating-point numbers
Definition: nppdefs.h:284
ZeroCrossing mode not supported.
Definition: nppdefs.h:160
Unsupported round mode.
Definition: nppdefs.h:171
Indicates that CUDA 6.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:256
Indicates that CUDA 2.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:247
Indicates that no operation was performed.
Definition: nppdefs.h:228
The NppiHOGConfig structure defines the configuration parameters for the HOG descriptor: ...
Definition: nppdefs.h:552
int numClassifiers
number of classifiers
Definition: nppdefs.h:569
2D Polar Point
Definition: nppdefs.h:405
int nHistogramBins
required number of histogram bins.
Definition: nppdefs.h:556
Two-parameter cubic filter (B=1/2, C=3/10)
Definition: nppdefs.h:98
Indicates that the quadrangle passed to one of affine warping functions doesn&#39;t have necessary proper...
Definition: nppdefs.h:230
NppsZCType
Definition: nppdefs.h:583
Step is less or equal zero.
Definition: nppdefs.h:208
NppiBorderType
Definition: nppdefs.h:510
One of the output image dimensions is less than 1 pixel.
Definition: nppdefs.h:175
float Npp32f
32-bit (IEEE) floating-point numbers
Definition: nppdefs.h:283
maximum
Definition: nppdefs.h:595
Npp32f rho
Definition: nppdefs.h:406
Indicates that CUDA 5.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:255
Definition: nppdefs.h:446
Definition: nppdefs.h:123
Indicates that CUDA 1.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:243
Definition: nppdefs.h:211
Definition: nppdefs.h:448
Definition: nppdefs.h:537
Definition: nppdefs.h:157
Definition: nppdefs.h:164
NppiAlphaOp
Definition: nppdefs.h:531
Definition: nppdefs.h:514
Divisor is equal to zero.
Definition: nppdefs.h:191
All values of the mask are zero.
Definition: nppdefs.h:184
Definition: nppdefs.h:567
Definition: nppdefs.h:155
Indicates that CUDA 3.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:250
NppHintAlgorithm
Definition: nppdefs.h:521
Definition: nppdefs.h:449
Definition: nppdefs.h:159
Generic Lanczos filtering with order 3.
Definition: nppdefs.h:101
Definition: nppdefs.h:113
Definition: nppdefs.h:199
Definition: nppdefs.h:141
Cubic interpolation.
Definition: nppdefs.h:95
2D Point
Definition: nppdefs.h:396
Two-parameter cubic filter (B=0, C=1/2)
Definition: nppdefs.h:97
Definition: nppdefs.h:165
struct NPP_ALIGN_8 Npp32fc
Complex Number This struct represents a single floating-point complex number.
Definition: nppdefs.h:538
Definition: nppdefs.h:219
Lanczos filtering.
Definition: nppdefs.h:100
The quadrangle is nonconvex or degenerates into triangle, line or point.
Definition: nppdefs.h:185
Successful operation (same as NPP_NO_ERROR)
Definition: nppdefs.h:225
Npp32f im
Imaginary part.
Definition: nppdefs.h:344
Definition: nppdefs.h:140
Number of levels for histogram is less than 2.
Definition: nppdefs.h:179
Definition: nppdefs.h:220
Two-parameter cubic filter (B=1, C=0)
Definition: nppdefs.h:96
Definition: nppdefs.h:263
Npp32s im
Imaginary part.
Definition: nppdefs.h:334
Definition: nppdefs.h:129
NppiDifferentialKernel
Differential Filter types.
Definition: nppdefs.h:138
int height
Rectangle height.
Definition: nppdefs.h:433

Copyright © 2009-2017 NVIDIA Corporation