Contents
- 1. CUDA for Tegra
- 2. Overview
- 3. Memory Management
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4. Porting Considerations
- 4.1. Memory Selection
- 4.2. Pinned Memory Guidelines on Tegra Systems with no I/O coherency
- 4.3. Effective Usage of Unified Memory on Tegra
- 4.4. GPU Selection
- 4.5. Synchronization Mechanism Selection
- 4.6. Multi-Process Service (MPS)
- 4.7. CUDA Features Not Supported on Tegra
- 4.8. GPUDirect RDMA
- 4.9. Additional Reads
- 5. EGL Interoperability
- 6. CUDA Upgradable Package for Jetson
- 7. CUDA Instrumentation Methods
- 8. CUDA Upgrade Package for Jetson
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9. cuDLA
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9.1. Developer Guide
- 9.1.1. Device Model
- 9.1.2. Loading and Querying Modules
- 9.1.3. Memory Model
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9.1.4. Task Execution and Synchronization Model
- 9.1.4.1. Task Execution
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9.1.4.2. Synchronization
- 9.1.4.2.1. Registering an external semaphore:
- 9.1.4.2.2. Events setup for cudlaSubmitTask()
- 9.1.4.2.3. Waiting on the signal event
- 9.1.4.2.4. Supported Synchronization Primitives in cuDLA
- 9.1.4.2.5. Setting NvSciSyncAttrKey_RequireDeterministicFences key in NvSciSyncAttrList
- 9.1.4.2.6. Timestamp Support for NvSciFence
- 9.1.4.2.7. Requesting Timestamp Support for NvSciSync Object
- 9.1.4.2.8. Extracting Timestamp Value from Fence
- 9.1.4.3. Fault Diagnostics
- 9.1.4.4. NOOP Submission
- 9.1.5. Error Reporting Model
- 9.2. Migrating from NvMediaDla to cuDLA
- 9.3. Profiling a cuDLA App
- 9.4. cuDLA Release Notes
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9.1. Developer Guide
- 10. CUDA integration with other SoC engines
- 11. CUDA C++ Coding Guidelines
- 12. Notices