NVIDIA Performance Primitives (NPP)  Version 10.1
nppdefs.h
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48 #ifndef NV_NPPIDEFS_H
49 #define NV_NPPIDEFS_H
50 
51 #include <stdlib.h>
52 #include <cuda_runtime.h>
53 
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62 
63 // Workaround for cuda_fp16.h C incompatibility
64 typedef
65 struct
66 {
67  short fp16;
68 }
69 Npp16f;
70 
71 typedef
72 struct
73 {
74  short fp16_0;
75  short fp16_1;
76 }
77 Npp16f_2;
78 
79 #define NPP_HALF_TO_NPP16F(pHalf) (* reinterpret_cast<Npp16f *>((void *)(pHalf)))
80 
81 // If this is a 32-bit Windows compile, don't align to 16-byte at all
82  // and use a "union-trick" to create 8-byte alignment.
83 #if defined(_WIN32) && !defined(_WIN64)
84 
85  // On 32-bit Windows platforms, do not force 8-byte alignment.
86  // This is a consequence of a limitation of that platform.
87  #define NPP_ALIGN_8
88  // On 32-bit Windows platforms, do not force 16-byte alignment.
89  // This is a consequence of a limitation of that platform.
90  #define NPP_ALIGN_16
91 
92 #else /* _WIN32 && !_WIN64 */
93 
94  #define NPP_ALIGN_8 __align__(8)
95  #define NPP_ALIGN_16 __align__(16)
96 
97 #endif /* !__CUDACC__ && _WIN32 && !_WIN64 */
98 
99 
107 typedef enum
108 {
119  NPPI_SMOOTH_EDGE = (int)0x8000000
121 
125 typedef enum
126 {
132 
136 typedef enum
137 {
140  NPP_MASK_SIZE_3_X_1 = 100, // leaving space for more 1 X N type enum values
142  NPP_MASK_SIZE_3_X_3 = 200, // leaving space for more N X 1 type enum values
149 } NppiMaskSize;
150 
155 typedef enum
156 {
160 
169 typedef enum
170 {
171  /* negative return-codes indicate errors */
173 
187 
237  NPP_ERROR = -2,
239 
240  /* success */
244  /* positive return-codes indicate warnings */
254 } NppStatus;
255 
256 
257 /*
258  * NOTE THAT THIS ENUM WILL BE DEPRECATED IN THE NEXT NPP RELEASE, CALL CUDA DIRECTLY TO FIND OUT THIS INFORMATION.
259  */
260 typedef enum
261 {
264  NPP_CUDA_1_0 = 100,
265  NPP_CUDA_1_1 = 110,
266  NPP_CUDA_1_2 = 120,
267  NPP_CUDA_1_3 = 130,
268  NPP_CUDA_2_0 = 200,
269  NPP_CUDA_2_1 = 210,
270  NPP_CUDA_3_0 = 300,
271  NPP_CUDA_3_2 = 320,
272  NPP_CUDA_3_5 = 350,
273  NPP_CUDA_3_7 = 370,
274  NPP_CUDA_5_0 = 500,
275  NPP_CUDA_5_2 = 520,
276  NPP_CUDA_5_3 = 530,
277  NPP_CUDA_6_0 = 600,
278  NPP_CUDA_6_1 = 610,
279  NPP_CUDA_6_2 = 620,
280  NPP_CUDA_6_3 = 630,
281  NPP_CUDA_7_0 = 700,
282  NPP_CUDA_7_2 = 720,
285 
286 typedef struct
287 {
288  int major;
289  int minor;
290  int build;
292 
298 typedef unsigned char Npp8u;
299 typedef signed char Npp8s;
300 typedef unsigned short Npp16u;
301 typedef short Npp16s;
302 typedef unsigned int Npp32u;
303 typedef int Npp32s;
304 typedef unsigned long long Npp64u;
305 typedef long long Npp64s;
306 typedef float Npp32f;
307 typedef double Npp64f;
314 typedef struct __align__(2)
315 {
316  Npp8u re;
317  Npp8u im;
319 
324 typedef struct __align__(4)
325 {
326  Npp16u re;
327  Npp16u im;
329 
334 typedef struct __align__(4)
335 {
336  Npp16s re;
337  Npp16s im;
339 
344 typedef struct NPP_ALIGN_8
345 {
346  Npp32u re;
347  Npp32u im;
348 } Npp32uc;
349 
354 typedef struct NPP_ALIGN_8
355 {
356  Npp32s re;
357  Npp32s im;
358 } Npp32sc;
359 
364 typedef struct NPP_ALIGN_8
365 {
366  Npp32f re;
367  Npp32f im;
368 } Npp32fc;
369 
374 typedef struct NPP_ALIGN_16
375 {
376  Npp64s re;
377  Npp64s im;
378 } Npp64sc;
379 
384 typedef struct NPP_ALIGN_16
385 {
386  Npp64f re;
387  Npp64f im;
388 } Npp64fc;
389 
392 #define NPP_MIN_8U ( 0 )
393 #define NPP_MAX_8U ( 255 )
394 #define NPP_MIN_16U ( 0 )
395 #define NPP_MAX_16U ( 65535 )
396 #define NPP_MIN_32U ( 0 )
397 #define NPP_MAX_32U ( 4294967295U )
398 #define NPP_MIN_64U ( 0 )
399 #define NPP_MAX_64U ( 18446744073709551615ULL )
401 #define NPP_MIN_8S (-127 - 1 )
402 #define NPP_MAX_8S ( 127 )
403 #define NPP_MIN_16S (-32767 - 1 )
404 #define NPP_MAX_16S ( 32767 )
405 #define NPP_MIN_32S (-2147483647 - 1 )
406 #define NPP_MAX_32S ( 2147483647 )
407 #define NPP_MAX_64S ( 9223372036854775807LL )
408 #define NPP_MIN_64S (-9223372036854775807LL - 1)
410 #define NPP_MINABS_32F ( 1.175494351e-38f )
411 #define NPP_MAXABS_32F ( 3.402823466e+38f )
412 #define NPP_MINABS_64F ( 2.2250738585072014e-308 )
413 #define NPP_MAXABS_64F ( 1.7976931348623158e+308 )
419 typedef struct
420 {
421  int x;
422  int y;
423 } NppiPoint;
424 
428 typedef struct {
429  Npp32f rho;
430  Npp32f theta;
431 } NppPointPolar;
432 
438 typedef struct
439 {
440  int width;
441  int height;
442 } NppiSize;
443 
451 typedef struct
452 {
453  int x;
454  int y;
455  int width;
456  int height;
457 } NppiRect;
458 
459 typedef enum
460 {
464 } NppiAxis;
465 
466 typedef enum
467 {
473 } NppCmpOp;
474 
488 typedef enum
489 {
502 
513 
523 
524  /*
525  * Other rounding modes supported by IEEE-754 (2008) floating-point standard:
526  *
527  * - NPP_ROUND_TOWARD_INFINITY // ceiling
528  * - NPP_ROUND_TOWARD_NEGATIVE_INFINITY // floor
529  *
530  */
531 } NppRoundMode;
532 
533 typedef enum
534 {
542 
543 
544 typedef enum {
549 
550 /*
551  * Alpha composition controls.
552  */
553 
554 typedef enum {
568 } NppiAlphaOp;
569 
570 
575 typedef struct
576 {
577  int cellSize;
581 } NppiHOGConfig;
582 
583 #define NPP_HOG_MAX_CELL_SIZE (16)
584 #define NPP_HOG_MAX_BLOCK_SIZE (64)
585 #define NPP_HOG_MAX_BINS_PER_CELL (16)
586 #define NPP_HOG_MAX_CELLS_PER_DESCRIPTOR (256)
587 #define NPP_HOG_MAX_OVERLAPPING_BLOCKS_PER_DESCRIPTOR (256)
588 #define NPP_HOG_MAX_DESCRIPTOR_LOCATIONS_PER_CALL (128)
590 typedef struct
591 {
593  Npp32s * classifiers;
596  Npp32s * counterDevice;
598 
599 typedef struct
600 {
602  Npp32s * haarBuffer;
605 
606 typedef enum {
610 } NppsZCType;
611 
612 typedef enum {
616 
617 typedef enum {
621 } NppiNorm;
622 
628 typedef struct
629 {
630  void * pData; // device memory pointer to the image
631  int nStep; // step size
632  NppiSize oSize; // width and height of the image
634 
640 typedef struct
641 {
642  cudaStream_t hStream;
643  int nCudaDeviceId; /* From cudaGetDevice() */
644  int nMultiProcessorCount; /* From cudaGetDeviceProperties() */
645  int nMaxThreadsPerMultiProcessor; /* From cudaGetDeviceProperties() */
646  int nMaxThreadsPerBlock; /* From cudaGetDeviceProperties() */
647  size_t nSharedMemPerBlock; /* From cudaGetDeviceProperties */
648  int nCudaDevAttrComputeCapabilityMajor; /* From cudaGetDeviceAttribute() */
649  int nCudaDevAttrComputeCapabilityMinor; /* From cudaGetDeviceAttribute() */
653 
654 #ifdef __cplusplus
655 } /* extern "C" */
656 #endif
657 
660 #endif /* NV_NPPIDEFS_H */
NppGpuComputeCapability
Definition: nppdefs.h:260
Definition: nppdefs.h:470
Definition: nppdefs.h:563
Definition: nppdefs.h:221
Definition: nppdefs.h:227
Definition: nppdefs.h:179
Speed reduction due to uncoalesced memory accesses warning.
Definition: nppdefs.h:252
Channel of interest is not 1, 2, or 3.
Definition: nppdefs.h:207
NppiMaskSize
Fixed filter-kernel sizes.
Definition: nppdefs.h:136
Indicates that CUDA 7.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:281
Npp32f re
Real part.
Definition: nppdefs.h:366
int nMaxThreadsPerMultiProcessor
Definition: nppdefs.h:645
Definition: nppdefs.h:71
Indicates that CUDA 6.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:278
Image pixels are constant for quality index.
Definition: nppdefs.h:190
Definition: nppdefs.h:540
Definition: nppdefs.h:148
Npp32u im
Imaginary part.
Definition: nppdefs.h:347
struct NPP_ALIGN_8 Npp32uc
Complex Number This struct represents an unsigned int complex number.
int height
Rectangle height.
Definition: nppdefs.h:441
Round to the nearest even integer.
Definition: nppdefs.h:500
Definition: nppdefs.h:145
General image descriptor.
Definition: nppdefs.h:628
int haarBufferSize
size of the buffer
Definition: nppdefs.h:601
Definition: nppdefs.h:462
Indicates that CUDA 1.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:266
unsigned char Npp8u
8-bit unsigned chars
Definition: nppdefs.h:298
Definition: nppdefs.h:139
Definition: nppdefs.h:180
Definition: nppdefs.h:234
Definition: nppdefs.h:229
Definition: nppdefs.h:186
struct __align__(2)
Complex Number This struct represents an unsigned char complex number.
Definition: nppdefs.h:314
int nCudaDeviceId
Definition: nppdefs.h:643
Complex Number This struct represents an unsigned int complex number.
Definition: nppdefs.h:344
Definition: nppdefs.h:539
int y
y-coordinate of upper left corner (lowest memory address).
Definition: nppdefs.h:454
int nStep
Definition: nppdefs.h:631
sum
Definition: nppdefs.h:619
Npp64f re
Real part.
Definition: nppdefs.h:386
Definition: nppdefs.h:184
Definition: nppdefs.h:143
Definition: nppdefs.h:144
Indicates that CUDA 5.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:275
Definition: nppdefs.h:546
int y
y-coordinate.
Definition: nppdefs.h:422
Indicates that CUDA 1.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:265
int nCudaDevAttrComputeCapabilityMajor
Definition: nppdefs.h:648
NppiAxis
Definition: nppdefs.h:459
Definition: nppdefs.h:238
Definition: nppdefs.h:178
Definition: nppdefs.h:183
Definition: nppdefs.h:218
cudaStream_t hStream
Definition: nppdefs.h:642
The given ROI has no interestion with either the source or destination ROI.
Definition: nppdefs.h:248
NppiBayerGridPosition
Bayer Grid Position Registration.
Definition: nppdefs.h:125
Npp64s re
Real part.
Definition: nppdefs.h:376
NppiSize detectionWindowSize
detection window size (pixels).
Definition: nppdefs.h:580
Definition: nppdefs.h:185
sign change XOR
Definition: nppdefs.h:608
AC Table.
Definition: nppdefs.h:614
NppStatus
Error Status Codes.
Definition: nppdefs.h:169
Definition: nppdefs.h:226
Bad or unsupported number of channels.
Definition: nppdefs.h:206
Npp8uc
Definition: nppdefs.h:318
Image size isn&#39;t multiple of two.
Definition: nppdefs.h:250
Definition: nppdefs.h:463
Definition: nppdefs.h:565
Definition: nppdefs.h:599
Indicates that CUDA 6.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:279
Npp32f theta
Definition: nppdefs.h:430
Definition: nppdefs.h:109
Definition: nppdefs.h:566
Npp32u re
Real part.
Definition: nppdefs.h:346
int nCudaDevAttrComputeCapabilityMinor
Definition: nppdefs.h:649
Wrong order of the destination channels.
Definition: nppdefs.h:200
Complex Number This struct represents a long long complex number.
Definition: nppdefs.h:374
Npp32s * haarBuffer
buffer
Definition: nppdefs.h:602
Indicates that CUDA 3.5 capable device is machine&#39;s default device.
Definition: nppdefs.h:272
sign change count_0
Definition: nppdefs.h:609
Definition: nppdefs.h:461
int nMaxThreadsPerBlock
Definition: nppdefs.h:646
Npp64s im
Imaginary part.
Definition: nppdefs.h:377
Npp32s re
Real part.
Definition: nppdefs.h:356
Definition: nppdefs.h:232
Step value is not pixel multiple.
Definition: nppdefs.h:195
Linear interpolation.
Definition: nppdefs.h:111
2D Size This struct typically represents the size of a a rectangular region in two space...
Definition: nppdefs.h:438
NppCmpOp
Definition: nppdefs.h:466
Definition: nppdefs.h:545
Definition: nppdefs.h:138
size_t nSharedMemPerBlock
Definition: nppdefs.h:647
Npp64f im
Imaginary part.
Definition: nppdefs.h:387
Definition: nppdefs.h:220
Definition: nppdefs.h:535
Definition: nppdefs.h:564
Round towards zero (truncation).
Definition: nppdefs.h:521
square root of sum of squares
Definition: nppdefs.h:620
Size of the rectangle region is less than or equal to 1.
Definition: nppdefs.h:203
Definition: nppdefs.h:556
Processed data is corrupted.
Definition: nppdefs.h:199
int x
x-coordinate.
Definition: nppdefs.h:421
Definition: nppdefs.h:468
Indicates that CUDA 5.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:274
Definition: nppdefs.h:235
Definition: nppdefs.h:142
struct NPP_ALIGN_16 Npp64sc
Complex Number This struct represents a long long complex number.
Number of levels for LUT is less than 2.
Definition: nppdefs.h:197
int width
Rectangle width.
Definition: nppdefs.h:440
int build
Build number.
Definition: nppdefs.h:290
int x
x-coordinate of upper left corner (lowest memory address).
Definition: nppdefs.h:453
Definition: nppdefs.h:536
Definition: nppdefs.h:141
Definition: nppdefs.h:538
Definition: nppdefs.h:233
struct NPP_ALIGN_16 Npp64fc
Complex Number This struct represents a double floating-point complex number.
struct NPP_ALIGN_8 Npp32sc
Complex Number This struct represents a signed int complex number.
int nReserved1
Definition: nppdefs.h:651
Indicates that CUDA 2.1 capable device is machine&#39;s default device.
Definition: nppdefs.h:269
long long Npp64s
64-bit signed integers
Definition: nppdefs.h:305
Definition: nppdefs.h:559
int cellSize
square cell size (pixels).
Definition: nppdefs.h:577
Definition: nppdefs.h:217
Definition: nppdefs.h:219
int major
Major version number.
Definition: nppdefs.h:288
Definition: nppdefs.h:562
int Npp32s
32-bit signed integers
Definition: nppdefs.h:303
sign change
Definition: nppdefs.h:607
Definition: nppdefs.h:567
Definition: nppdefs.h:547
Lower bound is larger than upper bound.
Definition: nppdefs.h:214
int minor
Minor version number.
Definition: nppdefs.h:289
NppiInterpolationMode
Filtering methods.
Definition: nppdefs.h:107
Divisor is zero however does not terminate the execution.
Definition: nppdefs.h:246
Round according to financial rule.
Definition: nppdefs.h:511
The given quadrangle has no intersection with either the source or destination ROI.
Definition: nppdefs.h:249
short fp16_1
Definition: nppdefs.h:75
Unallowable values of the transformation coefficients.
Definition: nppdefs.h:204
Alias name for NPP_RND_ZERO.
Definition: nppdefs.h:522
Definition: nppdefs.h:231
2D Rectangle This struct contains position and size information of a rectangle in two space...
Definition: nppdefs.h:451
Definition: nppdefs.h:64
DC Table.
Definition: nppdefs.h:613
Indicates that CUDA 7.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:282
void * pData
Definition: nppdefs.h:630
NppiSize classifierSize
Definition: nppdefs.h:595
Error free operation.
Definition: nppdefs.h:241
Indicates that no CUDA capable device was found.
Definition: nppdefs.h:263
Npp16uc
Definition: nppdefs.h:328
Super sampling.
Definition: nppdefs.h:116
Stride is less than the row length.
Definition: nppdefs.h:211
int width
Rectangle width.
Definition: nppdefs.h:455
Definition: nppdefs.h:230
Npp16sc
Definition: nppdefs.h:338
short fp16
Definition: nppdefs.h:67
Indicates that CUDA 3.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:270
Number overflows the upper or lower limit of the data type.
Definition: nppdefs.h:194
unsigned short Npp16u
16-bit unsigned integers
Definition: nppdefs.h:300
NppiNorm
Definition: nppdefs.h:617
Indicates that CUDA 1.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:267
Alias name for NPP_RND_NEAR.
Definition: nppdefs.h:501
NPP stream context structure must be filled in by application.
Definition: nppdefs.h:640
NppRoundMode
Rounding Modes.
Definition: nppdefs.h:488
size_t classifierStep
Definition: nppdefs.h:594
Indicates that the compute-capability query failed.
Definition: nppdefs.h:262
Definition: nppdefs.h:557
Npp32s * counterDevice
Definition: nppdefs.h:596
int histogramBlockSize
square histogram block size (pixels).
Definition: nppdefs.h:578
Indicates that CUDA 3.7 capable device is machine&#39;s default device.
Definition: nppdefs.h:273
Indicates that CUDA 6.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:280
Definition: nppdefs.h:175
Npp32s * classifiers
packed classifier data 40 bytes each
Definition: nppdefs.h:593
Definition: nppdefs.h:558
Definition: nppdefs.h:224
Definition: nppdefs.h:555
Definition: nppdefs.h:129
NppiHuffmanTableType
Definition: nppdefs.h:612
NppiSize oSize
Definition: nppdefs.h:632
short Npp16s
16-bit signed integers
Definition: nppdefs.h:301
Definition: nppdefs.h:128
unsigned int Npp32u
32-bit unsigned integers
Definition: nppdefs.h:302
Anchor point is outside mask.
Definition: nppdefs.h:213
Definition: nppdefs.h:222
signed char Npp8s
8-bit signed chars
Definition: nppdefs.h:299
Definition: nppdefs.h:223
unsigned long long Npp64u
64-bit unsigned integers
Definition: nppdefs.h:304
Nearest neighbor filtering.
Definition: nppdefs.h:110
Definition: nppdefs.h:147
Smooth edge filtering.
Definition: nppdefs.h:119
Alias name for NPP_RND_FINANCIAL.
Definition: nppdefs.h:512
Illegal channel index.
Definition: nppdefs.h:210
Default registration position.
Definition: nppdefs.h:127
double Npp64f
64-bit floating-point numbers
Definition: nppdefs.h:307
ZeroCrossing mode not supported.
Definition: nppdefs.h:177
Unsupported round mode.
Definition: nppdefs.h:188
Indicates that CUDA 6.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:277
Indicates that CUDA 2.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:268
Indicates that no operation was performed.
Definition: nppdefs.h:245
The NppiHOGConfig structure defines the configuration parameters for the HOG descriptor: ...
Definition: nppdefs.h:575
Indicates that CUDA 7.5 or better is machine&#39;s default device.
Definition: nppdefs.h:283
int numClassifiers
number of classifiers
Definition: nppdefs.h:592
2D Polar Point
Definition: nppdefs.h:428
int nHistogramBins
required number of histogram bins.
Definition: nppdefs.h:579
Two-parameter cubic filter (B=1/2, C=3/10)
Definition: nppdefs.h:115
Indicates that the quadrangle passed to one of affine warping functions doesn&#39;t have necessary proper...
Definition: nppdefs.h:247
NppsZCType
Definition: nppdefs.h:606
int nMultiProcessorCount
Definition: nppdefs.h:644
Step is less or equal zero.
Definition: nppdefs.h:225
NppiBorderType
Definition: nppdefs.h:533
One of the output image dimensions is less than 1 pixel.
Definition: nppdefs.h:192
float Npp32f
32-bit (IEEE) floating-point numbers
Definition: nppdefs.h:306
maximum
Definition: nppdefs.h:618
Npp32f rho
Definition: nppdefs.h:429
Indicates that CUDA 5.3 capable device is machine&#39;s default device.
Definition: nppdefs.h:276
Definition: nppdefs.h:469
Definition: nppdefs.h:140
Indicates that CUDA 1.0 capable device is machine&#39;s default device.
Definition: nppdefs.h:264
Definition: nppdefs.h:228
int nReserved0
Definition: nppdefs.h:650
Definition: nppdefs.h:471
Definition: nppdefs.h:560
Definition: nppdefs.h:174
Definition: nppdefs.h:181
NppiAlphaOp
Definition: nppdefs.h:554
Definition: nppdefs.h:537
Divisor is equal to zero.
Definition: nppdefs.h:208
All values of the mask are zero.
Definition: nppdefs.h:201
Definition: nppdefs.h:590
Definition: nppdefs.h:172
Indicates that CUDA 3.2 capable device is machine&#39;s default device.
Definition: nppdefs.h:271
NppHintAlgorithm
Definition: nppdefs.h:544
Definition: nppdefs.h:472
Definition: nppdefs.h:176
Generic Lanczos filtering with order 3.
Definition: nppdefs.h:118
Definition: nppdefs.h:130
Definition: nppdefs.h:216
Definition: nppdefs.h:158
Cubic interpolation.
Definition: nppdefs.h:112
2D Point
Definition: nppdefs.h:419
Two-parameter cubic filter (B=0, C=1/2)
Definition: nppdefs.h:114
Definition: nppdefs.h:182
struct NPP_ALIGN_8 Npp32fc
Complex Number This struct represents a single floating-point complex number.
Definition: nppdefs.h:561
Definition: nppdefs.h:236
Lanczos filtering.
Definition: nppdefs.h:117
short fp16_0
Definition: nppdefs.h:74
The quadrangle is nonconvex or degenerates into triangle, line or point.
Definition: nppdefs.h:202
Successful operation (same as NPP_NO_ERROR)
Definition: nppdefs.h:242
Npp32f im
Imaginary part.
Definition: nppdefs.h:367
Definition: nppdefs.h:157
Number of levels for histogram is less than 2.
Definition: nppdefs.h:196
Definition: nppdefs.h:237
Two-parameter cubic filter (B=1, C=0)
Definition: nppdefs.h:113
Definition: nppdefs.h:286
Npp32s im
Imaginary part.
Definition: nppdefs.h:357
Definition: nppdefs.h:146
NppiDifferentialKernel
Differential Filter types.
Definition: nppdefs.h:155
int height
Rectangle height.
Definition: nppdefs.h:456

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