◆ Use Cases for BESS
◆ Document History
| Version | Date | Description |
|---|---|---|
| 0.1 | 2026-01-07 | Initial draft for internal alignment |
| 0.2 | 2026-01-23 | Internal review |
| 0.3 | 2026-02-17 | DCE feedback incorporated: IEEE 2800 alignment, expanded test criteria and deliverables, NERC compliance, Test Results Templates |
| 0.4 | 2026-02-19 | Public release |
1 Introduction
This document defines the partner-run qualification process for a Battery Energy Storage System (BESS) intended to support AI load buffering, demand response (DR), and low voltage ride-through (LVRT) in grid-connected and islanded onsite generation modes.
The goal is to verify the availability and performance of key requirements for a grid-forming power conversion system (PCS)-based BESS including: dynamic real/reactive power response, current limiting behavior, ride-through behavior, islanded stability, black start, seamless grid/island transitions, telemetry, and control transparency.
BESS AC terminals (PCS inclusive). Everything "outside the BESS AC terminals" (site transformers, line reactors, switchgear, relays, generators, and campus control systems) is not physically qualified here. However, the partner must provide models and evidence sufficient for NVIDIA to validate site-level integration.
Passing qualification does not imply site-level stability. However, failure to demonstrate stability across the defined SCR, impedance, and load envelopes constitutes BESS non-qualification regardless of downstream integration.
2 General Expectations
Partners must follow this guideline exactly and submit results using the provided data template (to be provided as an .xlsx). Submissions must be clear, complete, and technically defensible.
Minimum Expectations
- All acronyms defined on first use
- All tests include raw time-series data at required sampling rates
- All plots include axis units, ranges, and timestamps
- Any deviation from requirements requires a written deviation request and proposed mitigation
- Partner must provide both:
- Hardware test evidence (bench, HIL, factory test, or field test), and
- Model evidence (EMT modeling + small-signal) for untestable edge cases
If a capability is claimed, it must be demonstrated with data and/or validated models.
Confidentiality
All materials provided under this qualification process are treated as NVIDIA Confidential and subject to applicable non-disclosure agreements.
- Partners may designate proprietary implementation details (e.g., controller source code, internal firmware) as restricted
- Measured performance data, test results, and qualification outcomes are not considered proprietary
- Encrypted or compiled models are acceptable, provided they are runnable and allow modification of external grid and load parameters
- Claims of confidentiality may not be used to withhold data required to verify compliance
3 BESS Qualification Overview
Step 1: Product Requirements Document (PRD) Review
Partner must respond to each PRD requirement line with:
- Compliant / Non-compliant / Exception (C, D, or E)
- For non-compliance: current behavior, roadmap, workaround, and risk
- For exceptions: explain the technical substitute and results
- Reference to specific evidence: test ID, plot, model, or certificate
Example PRD Response Format
| Requirement ID | Item | Description | Partner Response |
|---|---|---|---|
| CTRL-REQ-01 | Grid-forming | PCS shall operate grid-forming in island mode without PLL dependency | Compliant. Evidence: Test 9, EMT case E-4 |
| PERF-REQ-02 | Ramp limit | Demonstrate active ramp-rate smoothing to buffer the source from sudden AI load swings. The system must maintain constant stability between the source and the load, ensuring no oscillations or control 'hunting' occur during rapid power transitions or under normal load conditions. | Compliant. Evidence: Test 5 |
Since the qualification boundary is at BESS AC terminals, "POI ramp" requirements are verified using an approved POI proxy: a commanded P profile equivalent to the required POI shaping, and/or EMT verification using partner-provided models.
Step 2: Materials, Safety, and Compliance Disclosure
Partner must complete disclosure tables for:
2.1 Battery and PCS Materials and Safety
- Cell chemistry, enclosure type, fire detection/suppression approach
- Cooling method (air/liquid), coolant type (if applicable)
- Dielectrics/insulation class for major components
- Hazardous materials declaration (electrolyte class, refrigerants)
2.2 Standards and Regulatory Compliance Evidence
Provide certificates or reports for:
- UL 9540 / UL 9540A (or equivalent) status
- NFPA 855 alignment statement
- IEEE 2800 functional alignment statement (even if not certified)
- CE/UKCA (where applicable)
- RoHS/REACH
- EMC compliance evidence relevant to PCS
Step 3: Core Requirements Availability
A subset of requirements are designated Core Requirements representing minimum essential capabilities to pass qualification.
Table 1. Core Requirements (Minimum)
| No. | Core Requirement | Requirement ID | Minimum Requirement |
|---|---|---|---|
| 1 | Grid-forming capability | CTRL-CORE-01 | PCS shall operate grid-forming in island mode and during transitions. Loss of external voltage reference shall not induce mode switching or control topology change. No PLL participation in islanded steady-state or transients. Voltage source behavior under current limit. Defined virtual impedance or equivalent mechanism. |
| 2 | AI buffering dynamic response | PERF-CORE-01 | Demonstrate active ramp-rate smoothing to buffer the source from sudden AI load swings. The system must maintain constant stability between the source and the load, ensuring no oscillations or control 'hunting' occur during rapid power transitions or under normal load conditions. |
| 3 | Current limit behavior | PERF-CORE-02 | Current limiting shall be predictable: no unstable oscillation, no uncontrolled voltage collapse in modeled grid conditions |
| 4 | LVRT/HVRT | GRID-CORE-01 | Support IEEE 1547-2018 ride-through behavior as baseline; utility curves may supersede |
| 5 | Reactive power support | GRID-CORE-02 | Provide voltage support via Q within PCS current limits; document Q priority rules |
| 6 | Seamless grid/island transition | MODE-CORE-01 | Demonstrate controlled transitions without loss of synchronism or unstable control mode hunting. Models that cannot reproduce hardware behavior within stated tolerances are invalid. |
| 7 | Black start | MODE-CORE-02 | Demonstrate black-start energization of a dead bus and stable V/f regulation |
| 8 | Telemetry and controls | TELE-CORE-01 | Real-time reporting of V, I, P, Q, f, SOC, alarms, and limit states. Must support 3 concurrent Modbus TCP connections with all points being polled at 1 second frequency. SOC values must be included in all telemetry reporting. |
| 9 | Control transparency artifacts | MODEL-CORE-01 | Provide EMT model + dq impedance vs frequency + Nyquist/passivity artifacts. Also, comply with NERC Reliability Guidelines. |
| 10 | DR dispatch capability | OPS-CORE-01 | Follow dispatch setpoints with defined response time, ramp limits, and SOC reserve logic |
Step 4: Qualification Tests
This section defines test procedures and pass/fail criteria. All tests are performed at the BESS AC terminals unless explicitly stated as model-only.
Instrumentation Requirements (applies to all tests)
Minimum measurement accuracy:
- Voltage: ±0.2% of reading
- Current: ±0.5% of reading
- Power (P/Q): ±1.0% of reading
- Frequency: ±0.01 Hz
- Time sync: better than ±1 ms between channels
Minimum sampling:
- EMT-equivalent tests: ≥ 5 kHz preferred, ≥ 1 kHz minimum
- "Operational" tests: ≥ 10 Hz minimum
- All events must include pre-trigger (≥ 5 s) and post-trigger (≥ 20 s) unless otherwise specified
◆ Qualification Tests
Steps
- Operate PCS at 10%, 50%, 100% rated MW in grid-connected mode
- Record internal telemetry and compare to external revenue-grade meters
- Verify by demonstration reporting of: V, I, P, Q, f, SOC, PCS temperature, current limit flags, mode state
- Event logging shall be 1 ms precision
- Logs shall be held for 7 days
- P and Q error ≤ ±1% of reading across points
- Time alignment error ≤ 5 ms
- No missing channels, no "flatlined" sensors
Setup: Isolated test bus with configurable resistive/inductance/capacitance (RLC) load bank.
Steps
- Black start onto dead bus (if Test 10 not yet done, run reduced voltage)
- Hold voltage and frequency within the system's defined stability limits at a steady load
- Apply load steps: +10%, +20%, -20% of PCS rated MW
- Stable V/f with no sustained oscillation
- Voltage and frequency return to their steady-state range in a timely, well-damped manner, with no evidence of control hunting or marginal stability
- No protective trip
Steps
- Force the PCS into current limit using:
- Reduced-voltage condition on the test bus
- Commanded P and/or Q beyond the declared capability envelope
- Repeat for each priority configuration:
- Active power (P) priority
- Reactive power (Q) priority
- Partner default or "grid-support" mode
- Record P, Q, V, I, current-limit flags, and control-mode state variables
- PCS remains stable and controllable while in current limit
- PCS explicitly reports entry into and exit from current limit via telemetry
- Control priority and available headroom are observable and consistent with documented behavior
- Limit-cycle oscillation: Under steady-state operating conditions, no sustained oscillations shall be present, and PCS performance shall remain within all applicable generator and grid interconnection requirements.
- Control-mode hunting: More than one control-mode transition (e.g., P→Q→P, GFM→GFL, or equivalent) during a single current-limit event constitutes test failure.
- Voltage recovery behavior: Upon release from current limit, terminal voltage shall recover monotonically to its regulated setpoint. Any overshoot, undershoot, or oscillatory recovery exceeding ±5% of nominal voltage constitutes test failure.
Deliverables
- Demonstrate through EMT analysis
- P–Q capability map with clearly defined current-limit envelope
- Annotated time-series plots showing:
- Entry into current limit
- Behavior while limited
- Exit from current limit and voltage recovery
- Description of current-limit implementation and priority logic
Steps
- Operate PCS in grid-connected mode
- Apply a time-varying active power command profile that is representative of realistic AI workload ramps, including both short bursts and longer ramp intervals, and reaching ramp rates up to the vendor's declared AI-buffering capability. Partner must state the assumed IT load used for the test and demonstrate correct scaling of results.
- Record P, Q, V, I, and current-limit and control-mode state flags
- Tracking accuracy: Steady-state ramp tracking error ≤ 2% of commanded ramp magnitude
- Current limit: No entry into current limit during execution of required buffering profile
- Stability: No sustained oscillatory behavior induced by control interaction
- Sustained oscillation: Any clearly observable, sustained oscillatory behavior in measured P, Q, V, I, or frequency that indicates marginal or unstable control response during the ramp profile constitutes test failure, regardless of steady-state tracking accuracy.
- Current-limit interaction: Repeated or sustained entry into current limit, as indicated by PCS telemetry or limit-state flags, during execution of the required buffering profile constitutes test failure, unless explicitly declared as outside the partner's stated capability envelope.
- Ringing tolerance: Short-duration transient ringing (< 1 s) is acceptable only if it is monotonically decaying, does not re-enter current limit, and does not induce control-mode transitions.
This test does not, by itself, prove site POI compliance. It verifies that the PCS can execute the required buffering action when properly integrated.
Partner Provides
- EMT model of PCS + controls (compiled or encrypted acceptable, but must run)
- dq impedance curves vs frequency
- Nyquist or passivity evidence
Required EMT Case
- SCR: 2.0
- Grid impedance: High R/X ratio representative of inverter-dominated grids
- Topology: Grid-connected with upstream source modeled as weak voltage source
- Load: Constant power load with fast ramp characteristics
Disturbances to Apply
- AI buffering proxy ramps at ±20% IT load/s
- At least one grid disturbance event (voltage dip, impedance step, or partial islanding)
- Entry into and recovery from PCS current limit
- POI ramp compliance at ≤ 20% load/s for the defined workload profile
- No unstable oscillation modes across operating range
- System remains stable with no loss of synchronism
- No sustained oscillatory modes in the 1–30 Hz band
- No uncontrolled voltage collapse at the BESS terminals
- PCS transitions into and out of current limit in a controlled and documented manner
- Any unstable oscillation persisting > 1 second
- Voltage collapse or failure to recover to regulated operating point
- Control mode hunting or undefined control state transitions
- Model instability that prevents completion of the test scenario
This stress case may be performed model-only.
Failure in this case constitutes non-qualification, regardless of performance at higher SCR values. This test is intended to expose control fragility under realistic worst-case grid conditions expected in large AI campus deployments.
Steps
- Demonstrate dispatch steps at: 10%, 25%, 50%, 100% of DR committed MW
- Demonstrate ramp-limited dispatch (partner must implement ramp limits)
- Demonstrate SOC reserve policy: hold back X% SOC capacity reserved for LVRT/buffering
- Commanded MW achieved within specified response time (default: 2 s for fast DR, 60 s for slow DR)
- No violation of SOC reserve rules
- Clear state machine behavior when DR conflicts with LVRT
Deliverable: DR state machine diagram and priority rules
Steps
- Apply voltage sag and swell profiles at AC terminals (grid simulator or HIL):
- Multiple depth-duration points per IEEE 1547-2018 categories
- Observe whether PCS stays connected and how it prioritizes Q support
- No trip within IEEE envelope
- Correct trip outside envelope
- Q injection behavior documented and consistent
Steps
- Start grid-connected in buffering mode
- Execute intentional islanding event (open upstream breaker) while load present
- Maintain V/f and continue supplying load
- Resynchronize and reconnect to grid with controlled closing logic
- No unstable mode hunting
- No uncontrolled frequency drift
- Reclose without excessive inrush or protective trips
- Event logs show proper sequencing
Steps
- EMT model with GFM BESS as voltage master
- Generator modeled as droop-following source with realistic governor time constants
- Apply AI load proxy disturbance and show:
- BESS absorbs fast dynamics
- Generator picks up slower energy component
- Include N-1 generation event
- No sustained oscillation
- SOC drift controlled (see Test 11)
- Frequency and voltage remain within declared bounds
Steps
- PCS starts from de-energized condition
- Energize test bus to nominal voltage
- Pick up load in steps: 10%, 25%, 50% rated
- If using auxiliary supply, document requirements
- Stable energization
- No nuisance trips
- V/f regulation within declared bounds
Test duration: Minimum 24-hour continuous simulation or accelerated profile test.
Steps
- Run a 24-hour simulation or accelerated profile test:
- AI buffering proxy ramps applied intermittently throughout the test window
- Demand response dispatch events of varying magnitude and duration
- At least one LVRT or equivalent grid-disturbance event
- Declared SOC operating window and reserve thresholds enforced
- Net SOC drift: ≤ ±5% of usable SOC capacity, excluding declared DR events
- SOC bounds: Remain within partner-declared operating window at all times
- Energy prioritization: Explicit de-prioritization when approaching reserve thresholds
- Unbounded SOC drift: Exceeding ±5% without declared external energy imbalance
- Undefined reserve behavior: Loss of capability without explicit state transition
- Implicit behavior: SOC management relying on undocumented heuristics
Required Deliverables
- Time-series plots of SOC, P, Q, service state, and reserve flags
- Energy balance summary table (in/out, losses, DR energy, net drift)
- State machine diagram showing:
- Normal operation
- Reserve-threatened operation
- De-rating or service shedding behavior
- Event log with timestamped state transitions and priority changes
Oversizing battery capacity alone does not satisfy this requirement. SOC stability must be achieved through control logic and energy management, not nameplate capacity.
Required Deliverables
- EMT model package with instructions
- dq impedance vs frequency (magnitude and phase) in key operating points
- Nyquist plot or passivity assessment demonstrating stability margin
- Controller description: loops, bandwidths, current limit behavior
- Parameter list: droop coefficients, virtual impedance, inertia, PLL state (if any)
- Package is complete, runnable, and consistent with measured behavior
- No "black box with no stability evidence" accepted
Partners must submit:
- One Excel workbook (.xlsx) using the structure provided, with one tab per test
- One ZIP folder containing raw data files referenced by the workbook
- Optional PDFs only where explicitly requested (plots auto-generated from Excel preferred)
4 Business and Supply Chain Readiness
In addition to technical qualification, partners must demonstrate credible readiness to support AI-scale deployment timelines. This includes proven manufacturing throughput, realistic ramp capability, and supply chain resilience aligned with multi-hundred-MW to GW-scale deployments.
4.1 Demonstrated Manufacturing Throughput
Partners must disclose actual, historical production capability, not theoretical capacity.
Required Disclosures
- Annual PCS throughput delivered in the most recent 12-month period (MW/year)
- Largest single PCS or BESS deployment delivered to date (MW and delivery timeframe)
- Current factory locations supporting PCS production and final integration
- Current average and worst-case lead times for PCS delivery
Evidence Required
- Shipment records or customer references
- Factory acceptance test (FAT) throughput data
- Identification of binding constraints (labor, test infrastructure, power electronics, controls)
4.2 Scale Ramp Credibility (10× Within 24 Months)
Partners must present a credible, executable plan to scale PCS manufacturing throughput by an order of magnitude (10×) within 24 months.
Required Elements
- Baseline throughput (MW/year) and target throughput (MW/year)
- Time-phased ramp plan with quarterly milestones
- Critical path items: power semiconductor supply, control hardware, test infrastructure, labor
- Capital investments required (facilities, tooling, test equipment)
- Dependencies on single-source or constrained sub-suppliers
4.3 Supply Chain Resilience and Risk Disclosure
Required Disclosures
- Single-source components and mitigation plans
- Geographic concentration risks (manufacturing, sub-tiers)
- Long-lead components and committed capacity
- Inventory buffering strategy for critical components
- Exposure to export controls, trade restrictions, or geopolitical risk
4.4 Failure Mode Acknowledgment
Partners must explicitly identify scenarios in which scale targets cannot be met.
- Conditions under which throughput ramp would be delayed or capped
- Contingency plans and alternative sourcing strategies
- Clear articulation of commitments under accelerated demand scenarios
4.5 Industrial Standards and Regulatory Certificates
Partners must provide a list of industrial standards the system is designed to comply with (e.g., IEEE, IEC, GB), as well as test certificates (e.g., UL, CSA, CE, CCC) granted by countries or economic areas for installation and operation.
Lack of demonstrated historical throughput or absence of a credible scale-up plan constitutes business non-qualification, regardless of technical performance. This section is intended to surface manufacturing reality early, not after technical qualification.
5 Quality and Reliability
This section defines the minimum quality system evidence and reliability substantiation required for BESS qualification. The intent is to prevent "passes on paper" where functional tests succeed but field reliability is unacceptable.
5.1 Quality Management System and Traceability
Required Submissions
- QMS certification: ISO 9001 certificate (or equivalent), including scope and certified sites
- Change control process: Documented ECN/ECO process with revision control
- Supplier quality: Supplier qualification process, incoming inspection, SCAR workflow
- Traceability: Lot traceability for battery cells, power semiconductors, capacitors, magnetics, control boards
- Serialization: Unique serial numbers at rack, PCS, and critical subassembly level
- Nonconformance system: NCR process, RCA expectations, and closure criteria
- CAPA: Metrics and example packages from the last 12 months
5.2 Reliability Targets and Definitions
Minimum Required Declarations
- Availability target for the qualified configuration
- MTBF / MTTF definitions and calculation method
- Failure rate assumptions and confidence bounds
- AFR for major replaceable units (PCS power stage, controller, cooling system, BMS, contactors)
- Mission profile including ambient range, load profile, switching frequency, current-limit time fraction, SOC window
If the partner cannot defend reliability numbers under an AI buffering duty cycle, the system fails qualification regardless of lab functional results.
5.3 Reliability Model and Evidence Requirements
- Reliability block diagram (RBD) showing system topology and redundancy
- FMEA/DFMEA and PFMEA with top 20 risk items and mitigations
- Parts stress and thermal analysis for the PCS
- Reliability prediction method and justification
- Field reliability evidence (if product is deployed)
5.4 Environmental and Durability Qualification
- Thermal performance and derating curves
- Thermal cycling test results
- Vibration and shock testing (ISTA or IEC 60068 equivalent)
- Ingress protection (IP/NEMA rating evidence)
- Corrosion / contamination robustness
- Acoustic and mechanical resonance risks
5.5 Power Electronics Reliability and Protection Robustness
- Protection coordination philosophy inside the PCS
- Short-circuit and fault withstand capability
- Grid disturbance robustness
- Harmonic and ripple limits
5.6 Battery System Reliability and Safety Monitoring
- Cell and module qualification basis
- BMS robustness and fault detection coverage
- Thermal management reliability
- Degradation model and capacity fade predictions, including degradation rates based on shallow discharges at a variety of SOC levels
- Maintenance intervals and remote diagnostics capability
5.7 Factory Acceptance, Production Testing, and Burn-In
- Factory Acceptance Test (FAT) procedure
- Production test coverage (every unit vs sampling)
- Burn-in or screening for infant mortality
- Calibration and metrology schedule
5.8 Serviceability, Spares, and Mean Time to Repair
- MTTR assumptions and basis
- Spare parts list with recommended on-site spares
- Replaceable unit strategy and hot-swap capability
- 24/7 remote support model and escalation process
- Event logging requirements and export format
5.9 Reporting Format and Acceptance Criteria
Partners must submit a single Quality and Reliability Package containing:
- QMS certificates and site scope
- Reliability model (RBD + assumptions) and results
- DFMEA/PFMEA top risks and mitigations
- Environmental qualification reports
- FAT and production test summaries
- Field reliability data with failure mode breakdown
- Maintenance plan, MTTR basis, and spares strategy
- Missing QMS/traceability evidence
- Reliability predictions not tied to a declared mission profile
- Failure to provide DFMEA/PFMEA and top-risk mitigations
- Field data contradicts claims without explanation and corrective plan
◆ Appendices
Appendix A: Data Submission Requirements
Every test must include:
- Raw time-series (CSV)
- Summary plots (PDF)
- Test configuration (single-line of test setup, controller settings, SOC)
- Pass/fail statement tied to criteria
- Known issues and deviations list
Appendix B: Core Requirements Checklist
Partner must fill out a one-page checklist mapping: Core Requirement → Test IDs → Evidence references.
Appendix C: Partner Model Package Requirements
Minimum:
- EMT model (PSCAD/EMTDC, RTDS, or equivalent), including control blocks
- dq impedance plots at:
- 10%, 50%, 100% P
- High and low Q
- Multiple SCR values
- Nyquist/passivity artifact and interpretation
- Version-controlled parameter export
Models that cannot reproduce hardware behavior within stated tolerances are invalid.