Abstract
This cuDNN 7.6.5 Developer Guide provides an overview of cuDNN features such as customizable data layouts, supporting flexible dimension ordering, striding, and subregions for the 4D tensors used as inputs and outputs to all of its routines. This flexibility allows easy integration into any neural network implementation.
For previously released cuDNN developer documentation, see cuDNN Archives.
1. Overview
NVIDIA cuDNN is a GPUaccelerated library of primitives for deep neural networks. It provides highly tuned implementations of routines arising frequently in DNN applications:
 Convolution forward and backward, including crosscorrelation
 Pooling forward and backward
 Softmax forward and backward
 Neuron activations forward and backward:
 Rectified linear (ReLU)
 Sigmoid
 Hyperbolic tangent (TANH)
 Tensor transformation functions
 LRN, LCN and batch normalization forward and backward
cuDNN's convolution routines aim for a performance that is competitive with the fastest GEMM (matrix multiply)based implementations of such routines, while using significantly less memory.
cuDNN features include customizable data layouts, supporting flexible dimension ordering, striding, and subregions for the 4D tensors used as inputs and outputs to all of its routines. This flexibility allows easy integration into any neural network implementation, and avoids the input/output transposition steps sometimes necessary with GEMMbased convolutions.
cuDNN offers a contextbased API that allows for easy multithreading and (optional) interoperability with CUDA streams.
2. Programming Model
The cuDNN Library exposes a Host API but assumes that for operations using the GPU, the necessary data is directly accessible from the device.
An application using cuDNN must initialize a handle to the library context by calling cudnnCreate(). This handle is explicitly passed to every subsequent library function that operates on GPU data. Once the application finishes using cuDNN, it can release the resources associated with the library handle using cudnnDestroy(). This approach allows the user to explicitly control the library's functioning when using multiple host threads, GPUs and CUDA Streams.
For example, an application can use cudaSetDevice to associate different devices with different host threads, and in each of those host threads, use a unique cuDNN handle that directs the library calls to the device associated with it. Thus the cuDNN library calls made with different handles will automatically run on different devices.
The device associated with a particular cuDNN context is assumed to remain unchanged between the corresponding cudnnCreate() and cudnnDestroy() calls. In order for the cuDNN library to use a different device within the same host thread, the application must set the new device to be used by calling cudaSetDevice() and then create another cuDNN context, which will be associated with the new device, by calling cudnnCreate().
cuDNN API Compatibility

Any patch release x.y.z is forward or backwardcompatible with applications built against another cuDNN patch release x.y.w (meaning, of the same major and minor version number, but having w!=z).

cuDNN minor releases beginning with cuDNN 7 are binary backwardcompatible with applications built against the same or earlier patch release (meaning, an app built against cuDNN 7.x is binary compatible with cuDNN library 7.y, where y>=x).

Applications compiled with a cuDNN version 7.y are not guaranteed to work with 7.x release when y > x.
3. Convolution Formulas
This section describes the various convolution formulas implemented in cuDNN convolution functions.
Term  Description 

$x$  Input (image) Tensor 
$w$  Weight Tensor 
$y$  Output Tensor 
$n$  Current Batch Size 
$c$  Current Input Channel 
$C$  Total Input Channels 
$H$  Input Image Height 
$W$  Input Image Width 
$k$  Current Output Channel 
$K$  Total Output Channels 
$p$  Current Output Height Position 
$q$  Current Output Width Position 
$G$  Group Count 
$\mathit{pad}$  Padding Value 
$u$  Vertical Subsample Stride (along Height) 
$\mathit{v}$  Horizontal Subsample Stride (along Width) 
${\mathit{dil}}_{\mathit{h}}$  Vertical Dilation (along Height) 
${\mathit{dil}}_{\mathit{w}}$  Horizontal Dilation (along Width) 
$r$  Current Filter Height 
$R$  Total Filter Height 
$s$  Current Filter Width 
$S$  Total Filter Width 
${C}_{g}$  $\frac{C}{G}$ 
${K}_{g}$  $\frac{K}{G}$ 
Normal Convolution (using crosscorrelation mode)
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{C}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p+r,\; q+s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with Padding
${x}_{\mathit{<0,\; <0}}\phantom{\rule{5px}{0ex}}=0$
${x}_{\mathit{>H,\; >W}}\phantom{\rule{5px}{0ex}}=0$
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{C}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p+rpad,\; q+spad}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with SubsampleStriding
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{C}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; (p*u)\; +\; r,\; (q*v)\; +\; s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution with Dilation
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{C}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p\; +\; (r*dilh),\; q\; +\; (s*dilw)}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
Convolution using Convolution Mode
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{C}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; c,\; p\; +\; r,\; q\; +\; s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,\; c,\; Rr1,\; Ss1}}$
Convolution using Grouped Convolution
${C}_{g}=\frac{C}{G}$
${K}_{g}=\frac{K}{G}$
${y}_{\mathit{n,\; k,\; p,\; q}}=\sum _{c}^{{C}_{g}}\phantom{\rule{5px}{0ex}}\sum _{r}^{R}\phantom{\rule{5px}{0ex}}\sum _{s}^{S}\phantom{\rule{10px}{0ex}}{x}_{\mathit{n,\; Cg*floor(k/Kg)+c,\; p+r,\; q+s}}\phantom{\rule{15px}{0ex}}\times \phantom{\rule{15px}{0ex}}{w}_{\mathit{k,c,r,s}}$
4. Notation
As of CUDNN v4 we have adopted a mathematicalyinspired notation for layer inputs and outputs using x,y,dx,dy,b,w for common layer parameters. This was done to improve readability and ease of understanding of the meaning of the parameters. All layers now follow a uniform convention as below:
In backpropagation routines the parameters keep their meanings.
5. Tensor Descriptor
The cuDNN Library describes data holding images, videos and any other data with contents with a generic nD tensor defined with the following parameters:

a dimension nbDims from 3 to 8

a data type (32bit floating point, 64 bitfloating point, 16 bit floating point...)

dimA integer array defining the size of each dimension

strideA integer array defining the stride of each dimension (for example, the number of elements to add to reach the next element from the same dimension)
The first dimension of the tensor defines the batch size n, and the second dimension defines the number of features maps c. This tensor definition allows for example to have some dimensions overlapping each others within the same tensor by having the stride of one dimension smaller than the product of the dimension and the stride of the next dimension. In cuDNN, unless specified otherwise, all routines will support tensors with overlapping dimensions for forward pass input tensors, however, dimensions of the output tensors cannot overlap. Even though this tensor format supports negative strides (which can be useful for data mirroring), cuDNN routines do not support tensors with negative strides unless specified otherwise.
5.1. WXYZ Tensor Descriptor
Tensor descriptor formats are identified using acronyms, with each letter referencing a corresponding dimension. In this document, the usage of this terminology implies:

all the strides are strictly positive

the dimensions referenced by the letters are sorted in decreasing order of their respective strides
5.2. 4D Tensor Descriptor
A 4D Tensor descriptor is used to define the format for batches of 2D images with 4 letters: N,C,H,W for respectively the batch size, the number of feature maps, the height and the width. The letters are sorted in decreasing order of the strides. The commonly used 4D tensor formats are:
 NCHW
 NHWC
 CHWN
5.3. 5D Tensor Description
A 5D Tensor descriptor is used to define the format of batch of 3D images with 5 letters: N,C,D,H,W for respectively the batch size, the number of feature maps, the depth, the height and the width. The letters are sorted in decreasing order of the strides. The commonly used 5D tensor formats are called:
 NCDHW
 NDHWC
 CDHWN
5.4. Fullypacked Tensors
A tensor is defined as XYZfullypacked if and only if:

the number of tensor dimensions is equal to the number of letters preceding the fullypacked suffix.

the stride of the ith dimension is equal to the product of the (i+1)th dimension by the (i+1)th stride.

the stride of the last dimension is 1.
5.5. Partiallypacked Tensors
The partially XYZpacked terminology only applies in the context of a tensor format described with a superset of the letters used to define a partiallypacked tensor. A WXYZ tensor is defined as XYZpacked if and only if:

the strides of all dimensions NOT referenced in the packed suffix are greater or equal to the product of the next dimension by the next stride.

the stride of each dimension referenced in the packed suffix in position i is equal to the product of the (i+1)st dimension by the (i+1)st stride.

if last tensor's dimension is present in the packed suffix, its stride is 1.
For example, a NHWC tensor WCpacked means that the c_stride is equal to 1 and w_stride is equal to c_dim x c_stride. In practice, the packed suffix is usually with slowest changing dimensions of a tensor but it is also possible to refer to a NCHW tensor that is only Npacked.
5.6. Spatially Packed Tensors
Spatiallypacked tensors are defined as partiallypacked in spatial dimensions.
For example, a spatiallypacked 4D tensor would mean that the tensor is either NCHW HWpacked or CNHW HWpacked.
5.7. Overlapping Tensors
A tensor is defined to be overlapping if iterating over a full range of dimensions produces the same address more than once.
In practice an overlapped tensor will have stride[i1] < stride[i]*dim[i] for some of the i from [1,nbDims] interval.
6. Data Layout Formats
This section describes how cuDNN Tensors are arranged in memory. See cudnnTensorFormat_t for enumerated Tensor format types.
6.1. Example
 N is the batch size; 1.
 C is the number of feature maps (i.e., number of channels); 64.
 H is the image height; 5.
 W is the image width; 4.
To keep the example simple, the image pixel elements are expressed as a sequence of integers, 0, 1, 2, 3, and so on. See Figure 1.
6.2. NCHW Memory Layout
 Beginning with the first channel (c=0), the elements are arranged contiguously in rowmajor order.
 Continue with second and subsequent channels until the elements of all the channels are laid out. See Figure 2.
 Proceed to the next batch (if N is > 1).
6.3. NHWC Memory Layout
 Begin with the first element of channel 0, then proceed to the first element of channel 1, and so on, until the first elements of all the C channels are laid out.
 Next, select the second element of channel 0, then proceed to the second element of channel 1, and so on, until the second element of all the channels are laid out.
 Follow the rowmajor order in channel 0 and complete all the elements. See Figure 3.
 Proceed to the next batch (if N is > 1).
6.4. NC/32HW32 Memory Layout
The NC/32HW32 is similar to NHWC, with a key difference. For the NC/32HW32 memory layout, the 64 channels are grouped into two groups of 32 channels each—first group consisting of channels c0 through c31, and the second group consisting of channels c32 through c63. Then each group is laid out using the NHWC format. See Figure 4.

Only the channel dimension, C, is grouped into x channels each.

When x = 1, each group has only one channel. Hence, the elements of one channel (i.e, one group) are arranged contiguously (in the rowmajor order), before proceeding to the next group (i.e., next channel). This is the same as NCHW format.

When x = C, then NC/xHWx is identical to NHWC, i.e., the entire channel depth C is considered as a single group. The case x = C can be thought of as vectorizing entire C dimension as one big vector, laying out all the Cs, followed by the remaining dimensions, just like NHWC.

The tensor format CUDNN_TENSOR_NCHW_VECT_C can also be interpreted in the following way: The NCHW INT8x32 format is really N x (C/32) x H x W x 32 (32 Cs for every W), just as the NCHW INT8x4 format is N x (C/4) x H x W x 4 (4 Cs for every W). Hence the "VECT_C" name  each W is a vector (4 or 32) of Cs.
7. Thread Safety
The library is thread safe and its functions can be called from multiple host threads, as long as threads to do not share the same cuDNN handle simultaneously.
8. Reproducibility (determinism)
By design, most of cuDNN's routines from a given version generate the same bitwise results across runs when executed on GPUs with the same architecture and the same number of SMs. However, bitwise reproducibility is not guaranteed across versions, as the implementation of a given routine may change. With the current release, the following routines do not guarantee reproducibility because they use atomic operations:

cudnnConvolutionBackwardFilter when CUDNN_CONVOLUTION_BWD_FILTER_ALGO_0 or CUDNN_CONVOLUTION_BWD_FILTER_ALGO_3 is used

cudnnConvolutionBackwardData when CUDNN_CONVOLUTION_BWD_DATA_ALGO_0 is used

cudnnPoolingBackward when CUDNN_POOLING_MAX is used

cudnnSpatialTfSamplerBackward
9. Scaling Parameters
dstValue = alpha*computedValue + beta*priorDstValue
When beta is zero, the output is not read and may contain uninitialized data (including NaN).
 float for HALF and FLOAT tensors, and
 double for DOUBLE tensors.
Type Conversion
When the data input x, the filter input w and the output y are all in INT8 data type, the function cudnnConvolutionBiasActivationForward() will perform the type conversion as shown in Figure 6:
10. Tensor Core Operations
The cuDNN v7 library introduced the acceleration of computeintensive routines using Tensor Core hardware on supported GPU SM versions. Tensor core operations are supported on the Volta and Turing GPU families.
10.1. Basics
Tensor core operations perform parallel floating point accumulation of multiple floating point product terms. Setting the math mode to CUDNN_TENSOR_OP_MATH via the cudnnMathType_t enumerator indicates that the library will use Tensor Core operations. This enumerator specifies the available options to enable the Tensor Core, and should be applied on a perroutine basis.
The default math mode is CUDNN_DEFAULT_MATH, which indicates that the Tensor Core operations will be avoided by the library. Because the CUDNN_TENSOR_OP_MATH mode uses the Tensor Cores, it is possible that these two modes generate slightly different numerical results due to different sequencing of the floating point operations.
For example, the result of multiplying two matrices using Tensor Core operations is very close to, but not always identical, the result achieved using a sequence of scalar floating point operations. For this reason, the cuDNN library requires an explicit user optin before enabling the use of Tensor Core operations.
However, experiments with training common deep learning models show negligible differences between using Tensor Core operations and scalar floating point paths, as measured by both the final network accuracy and the iteration count to convergence. Consequently, the cuDNN library treats both modes of operation as functionally indistinguishable, and allows for the scalar paths to serve as legitimate fallbacks for cases in which the use of Tensor Core operations is unsuitable.
Kernels using Tensor Core operations are available for both convolutions and RNNs.
See also Training with Mixed Precision.
10.2. Convolution Functions
10.2.1. Prerequisites
For the supported GPUs, the Tensor Core operations will be triggered for convolution functions only when cudnnSetConvolutionMathType() is called on the appropriate convolution descriptor by setting the mathType to CUDNN_TENSOR_OP_MATH or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION.
10.2.2. Supported Algorithms
10.2.3. Data And Filter Formats
The cuDNN library may use padding, folding, and NCHWtoNHWC transformations to call the Tensor Core operations. See Tensor Transformations.

Input, filter, and output descriptors (xDesc, yDesc, wDesc, dxDesc, dyDesc and dwDesc as applicable) are of the dataType = CUDNN_DATA_HALF (i.e., FP16). For FP32 dataType see FP32toFP16 Conversion.

The number of input and output feature maps (i.e., channel dimension C) is a multiple of 8. When the channel dimension is not a multiple of 8, see Padding.

The filter is of type CUDNN_TENSOR_NCHW or CUDNN_TENSOR_NHWC.

If using a filter of type CUDNN_TENSOR_NHWC, then the input, filter, and output data pointers (X, Y, W, dX, dY, and dW as applicable) are aligned to 128bit boundaries.
10.3. RNN Functions
10.3.1. Prerequisites
Tensor core operations will be triggered for these RNN functions only when cudnnSetRNNMatrixMathType() is called on the appropriate RNN descriptor setting mathType to CUDNN_TENSOR_OP_MATH or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION.
10.3.2. Supported Algorithms
10.3.3. Data And Filter Formats

For algo = CUDNN_RNN_ALGO_STANDARD:
 The hidden state size, input size and the batch size is a multiple of 8.
 All userprovided tensors, workspace, and reserve space are aligned to 128 bit boundaries.
 For FP16 input/output, the CUDNN_TENSOR_OP_MATH or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION is selected.
 For FP32 input/output, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION is selected.

For algo = CUDNN_RNN_ALGO_PERSIST_STATIC:
 The hidden state size and the input size is a multiple of 32.
 The batch size is a multiple of 8.
 If the batch size exceeds 96 (for forward training or inference) or 32 (for backward data), then the batch sizes constraints may be stricter, and large poweroftwo batch sizes may be needed.
 All userprovided tensors, workspace, and reserve space are aligned to 128 bit boundaries.
 For FP16 input/output, CUDNN_TENSOR_OP_MATH or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION is selected.
 For FP32 input/output, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION is selected.
See also Features Of RNN Functions.
10.4. Tensor Transformations
A few functions in the cuDNN library will perform transformations such as folding, padding, and NCHWtoNHWC conversion while performing the actual function operation. See below.
10.4.1. FP16 Data
Tensor Cores operate on FP16 input data with FP32 accumulation. The FP16 multiply leads to a fullprecision result that is accumulated in FP32 operations with the other products in a given dot product for a matrix with m x n x k dimensions. See Figure 7.
10.4.2. FP32toFP16 Conversion
The cuDNN API for allows the user to specify that FP32 input data may be copied and converted to FP16 data internally to use Tensor Core operations for potentially improved performance. This can be achieved by selecting CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION enum for cudnnMathType_t. In this mode, the FP32 tensors are internally downconverted to FP16, the Tensor Op math is performed, and finally upconverted to FP32 as outputs. See Figure 8.
For Convolutions
// Set the math type to allow cuDNN to use Tensor Cores: checkCudnnErr(cudnnSetConvolutionMathType(cudnnConvDesc, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION));
For RNNs
// Set the math type to allow cuDNN to use Tensor Cores: checkCudnnErr(cudnnSetRNNMatrixMathType(cudnnRnnDesc, CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION));
10.4.3. Padding
For packed NCHW data, when the channel dimension is not a multiple of 8, then the cuDNN library will pad the tensors as needed to enable Tensor Core operations. This padding is automatic for packed NCHW data in both the CUDNN_TENSOR_OP_MATH and the CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION cases.
// Set NCHW Tensor dimensions, not necessarily as multiples of eight (only the input tensor is shown here): int dimA[] = {1, 7, 32, 32}; int strideA[] = {7168, 1024, 32, 1};
10.4.4. Folding
In the folding operation the cuDNN library implicitly performs the formatting of input tensors and saves the input tensors in an internal workspace. This can lead to an acceleration of the call to Tensor Cores.
Folding enables the input tensors to be transformed to a format that the Tensor Cores support (i.e., no strides).
10.4.5. Conversion Between NCHW And NHWC
Tensor Cores require that the tensors be in NHWC data layout. Conversion between NCHW and NHWC is performed when the user requests Tensor Op math. However, as stated in Basics, a request to use Tensor Cores is just that, a request, and Tensor Cores may not be used in some cases. The cuDNN library converts between NCHW and NHWC if and only if Tensor Cores are requested and are actually used.
If your input (and output) are NCHW, then expect a layout change.
NonTensor Op convolutions will not perform conversions between NCHW and NHWC.
In very rare and difficulttoqualify cases that are a complex function of padding and filter sizes, it is possible that Tensor Ops are not enabled. In such cases, users should prepad.
10.5. Guidelines For A Deep Learning Compiler

Make sure that the convolution operation is eligible for Tensor Cores by avoiding any combinations of large padding and large filters.

Transform the inputs and filters to NHWC, prepad channel and batch size to be a multiple of 8.

Make sure that all userprovided tensors, workspace and reserve space are aligned to 128 bit boundaries.
11. GPU And Driver Requirements
For the latest compatibility software versions of the OS, CUDA, the CUDA driver, and the NVIDIA hardware, see the cuDNN Support Matrix.
12. Backward Compatibility And Deprecation Policy
When changing the API of an existing cuDNN function "foo" (usually to support some new functionality), first, a new routine "foo_v<n>" is created where n represents the cuDNN version where the new API is first introduced, leaving "foo" untouched. This ensures backward compatibility with the version n1 of cuDNN. At this point, "foo" is considered deprecated, and should be treated as such by users of cuDNN. We gradually eliminate deprecated and suffixed API entries over the course of a few releases of the library per the following policy:
As a rule of thumb, when a routine appears in two forms, one with a suffix and one with no suffix, the nonsuffixed entry is to be treated as deprecated. In this case, it is strongly advised that users migrate to the new suffixed API entry to guarantee backwards compatibility in the following cuDNN release. When a routine appears with multiple suffixes, the unsuffixed API entry is mapped to the higher numbered suffix. In that case, it is strongly advised to use the nonsuffixed API entry to guarantee backward compatibility with the following cuDNN release.
13. Grouped Convolutions
Basic Idea
Conceptually, in grouped convolutions the input channels and the filter channels are split into groupCount number of independent groups, with each group having a reduced number of channels. Convolution operation is then performed separately on these input and filter groups.
For example, consider the following: if the number of input channels is 4, and the number of filter channels of 12. For a normal, ungrouped convolution, the number of computation operations performed are 12*4.
If the groupCount is set to 2, then there are now two input channel groups of two input channels each, and two filter channel groups of six filter channels each.
As a result, each grouped convolution will now perform 2*6 computation operations, and two such grouped convolutions are performed. Hence the computation savings are 2x: (12*4)/(2*(2*6))
14. API Logging
cuDNN API logging is a tool that records all input parameters passed into every cuDNN API function call. This functionality is disabled by default, and can be enabled through methods described in this section.
The log output contains variable names, data types, parameter values, device pointers, process ID, thread ID, cuDNN handle, CUDA stream ID, and metadata such as time of the function call in microseconds.
When logging is enabled, the log output will be handled by the builtin default callback function. The user may also write their own callback function, and use the cudnnSetCallback() to pass in the function pointer of their own callback function. The following is a sample output of the API log.
Function cudnnSetActivationDescriptor() called:
mode: type=cudnnActivationMode_t; val=CUDNN_ACTIVATION_RELU (1);
reluNanOpt: type=cudnnNanPropagation_t; val=CUDNN_NOT_PROPAGATE_NAN (0);
coef: type=double; val=1000.000000;
Time: 20171121T14:14:21.366171 (0d+0h+1m+5s since start)
Process: 21264, Thread: 21264, cudnn_handle: NULL, cudnn_stream: NULL.
There are two methods to enable API logging.
Method 1: Using Environment Variables
See also Table 2 for the impact on performance of API logging using environment variables.
Environment variables  CUDNN_LOGINFO_DBG=0  CUDNN_LOGINFO_DBG=1 

CUDNN_LOGDEST_DBG not set 
No logging output No performance loss 
No logging output No performance loss 
CUDNN_LOGDEST_DB =NULL 
No logging output No performance loss 
No logging output No performance loss 
CUDNN_LOGDEST_DBG=stdout or stderr 
No logging output No performance loss 
Logging to stdout or stderr Some performance loss 
CUDNN_LOGDEST_DBG=filename.txt 
No logging output No performance loss 
Logging to filename.txt Some performance loss 
Method 2
Method 2: To use API function calls to enable API logging, refer to the API description of cudnnSetCallback() and cudnnGetCallback().
15. Features Of RNN Functions
For each of these terms, the shortform versions shown in the parenthesis are used in the tables below for brevity: CUDNN_RNN_ALGO_STANDARD (_ALGO_STANDARD), CUDNN_RNN_ALGO_PERSIST_STATIC (_ALGO_PERSIST_STATIC), CUDNN_RNN_ALGO_PERSIST_DYNAMIC (_ALGO_PERSIST_DYNAMIC), and CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION (_ALLOW_CONVERSION).
Functions  Input output layout supported  Supports variable sequence length in batch  Commonly supported 

cudnnRNNForwardInference  Only Sequence major, packed (nonpadded) 
Only with _ALGO_STANDARD Require input sequences descending sorted according to length 
Mode (cell type) supported: CUDNN_RNN_RELU, CUDNN_RNN_TANH, CUDNN_LSTM, CUDNN_GRUAlgo supported^{1} (see the table below for an elaboration on these algorithms): _ALGO_STANDARD, _ALGO_PERSIST_STATIC, _ALGO_PERSIST_DYNAMIC Math mode supported: CUDNN_DEFAULT_MATH,CUDNN_TENSOR_OP_MATH (will automatically fall back if run on preVolta or if algo doesn’t support Tensor Cores) _ALLOW_CONVERSION (may do down conversion to utilize Tensor Cores) Direction mode supported: CUDNN_UNIDIRECTIONAL,
RNN input mode: CUDNN_LINEAR_INPUT, CUDNN_SKIP_INPUT 
cudnnRNNForwardTraining  
cudnnRNNBackwardData  
cudnnRNNBackwardWeights  
cudnnRNNForwardInferenceEx 

Only with _ALGO_STANDARD For unpacked layout^{2}, no input sorting required. For packed layout, require input sequences descending sorted according to length 

cudnnRNNForwardTrainingEx  
cudnnRNNBackwardDataEx  
cudnnRNNBackwardWeightsEx 
Features  _ALGO_STANDARD  _ALGO_PERSIST_STATIC  _ALGO_PERSIST_DYNAMIC 

Half input
Single accumulation Half output 
Supported
Half intermediate storage Single accumulation 

Single input
Single accumulation Single output 
Supported
If running on Volta, with CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION^{!}, will downconvert and use half intermediate storage. Otherwise: Single intermediate storage Single accumulation 

Double input
Double accumulation Double output 
Supported
Double intermediate storage Double accumulation 
Not Supported  Supported
Double intermediate storage Double accumulation 
LSTM recurrent projection  Supported  Not Supported  Not Supported 
LSTM cell clipping  Supported  
Variable sequence length in batch  Supported  Not Supported  Not Supported 
Tensor Cores on Volta/Xavier 
Supported For half input/output, acceleration requires setting CUDNN_TENSOR_OP_MATH^{3} or CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION ^{3} Acceleration requires inputSize and hiddenSize to be a multiple of 8 For single input/output, acceleration requires setting CUDNN_TENSOR_OP_MATH_ALLOW_CONVERSION^{3} Acceleration requires inputSize and hiddenSize to be a multiple of 8 
Not Supported, will execute normally ignoring CUDNN_TENSOR_OP_MATH^{3} or _ALLOW_CONVERSION^{3}  
Other limitations  Max problem size is limited by GPU specifications.  Requires real time compilation through NVRTC 
16. Mixed Precision Numerical Accuracy
When the computation precision and the output precision are not the same, it is possible that the numerical accuracy will vary from one algorithm to the other.
For example, when the computation is performed in FP32 and the output is in FP16, the CUDNN_CONVOLUTION_BWD_FILTER_ALGO_0 (ALGO_0) has lower accuracy compared to the CUDNN_CONVOLUTION_BWD_FILTER_ALGO_1 (ALGO_1). This is because ALGO_0 does not use extra workspace, and is forced to accumulate the intermediate results in FP16, i.e., half precision float, and this reduces the accuracy. The ALGO_1, on the other hand, uses additional workspace to accumulate the intermediate values in FP32, i.e., full precision float.
17. Acknowledgments
Some of the cuDNN library routines were derived from code developed by others and are subject to the following:
17.1. University of Tennessee
Copyright (c) 2010 The University of Tennessee. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer listed in this license in the documentation and/or other materials provided with the distribution. * Neither the name of the copyright holders nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17.2. University of California, Berkeley
COPYRIGHT All contributions by the University of California: Copyright (c) 2014, The Regents of the University of California (Regents) All rights reserved. All other contributions: Copyright (c) 2014, the respective contributors All rights reserved. Caffe uses a shared copyright model: each contributor holds copyright over their contributions to Caffe. The project versioning records all such contribution and copyright details. If a contributor wants to further mark their specific copyright on a particular contribution, they should indicate their copyright solely in the commit message of the change when it is committed. LICENSE Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. CONTRIBUTION AGREEMENT By contributing to the BVLC/caffe repository through pullrequest, comment, or otherwise, the contributor releases their content to the license and copyright terms herein.
17.3. Facebook AI Research, New York
Copyright (c) 2014, Facebook, Inc. All rights reserved. Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. * Neither the name Facebook nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Additional Grant of Patent Rights "Software" means fbcunn software distributed by Facebook, Inc. Facebook hereby grants you a perpetual, worldwide, royaltyfree, nonexclusive, irrevocable (subject to the termination provision below) license under any rights in any patent claims owned by Facebook, to make, have made, use, sell, offer to sell, import, and otherwise transfer the Software. For avoidance of doubt, no license is granted under Facebookâ€™s rights in any patent claims that are infringed by (i) modifications to the Software made by you or a third party, or (ii) the Software in combination with any software or other technology provided by you or a third party. The license granted hereunder will terminate, automatically and without notice, for anyone that makes any claim (including by filing any lawsuit, assertion or other action) alleging (a) direct, indirect, or contributory infringement or inducement to infringe any patent: (i) by Facebook or any of its subsidiaries or affiliates, whether or not such claim is related to the Software, (ii) by any party if such claim arises in whole or in part from any software, product or service of Facebook or any of its subsidiaries or affiliates, whether or not such claim is related to the Software, or (iii) by any party relating to the Software; or (b) that any right in any patent claim of Facebook is invalid or unenforceable.
Notices
Notice
_{THE INFORMATION IN THIS GUIDE AND ALL OTHER INFORMATION CONTAINED IN NVIDIA DOCUMENTATION REFERENCED IN THIS GUIDE IS PROVIDED “AS IS.” NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, OR OTHERWISE WITH RESPECT TO THE INFORMATION FOR THE PRODUCT, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE. Notwithstanding any damages that customer might incur for any reason whatsoever, NVIDIA’s aggregate and cumulative liability towards customer for the product described in this guide shall be limited in accordance with the NVIDIA terms and conditions of sale for the product.}
_{THE NVIDIA PRODUCT DESCRIBED IN THIS GUIDE IS NOT FAULT TOLERANT AND IS NOT DESIGNED, MANUFACTURED OR INTENDED FOR USE IN CONNECTION WITH THE DESIGN, CONSTRUCTION, MAINTENANCE, AND/OR OPERATION OF ANY SYSTEM WHERE THE USE OR A FAILURE OF SUCH SYSTEM COULD RESULT IN A SITUATION THAT THREATENS THE SAFETY OF HUMAN LIFE OR SEVERE PHYSICAL HARM OR PROPERTY DAMAGE (INCLUDING, FOR EXAMPLE, USE IN CONNECTION WITH ANY NUCLEAR, AVIONICS, LIFE SUPPORT OR OTHER LIFE CRITICAL APPLICATION). NVIDIA EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS FOR SUCH HIGH RISK USES. NVIDIA SHALL NOT BE LIABLE TO CUSTOMER OR ANY THIRD PARTY, IN WHOLE OR IN PART, FOR ANY CLAIMS OR DAMAGES ARISING FROM SUCH HIGH RISK USES.}
_{NVIDIA makes no representation or warranty that the product described in this guide will be suitable for any specified use without further testing or modification. Testing of all parameters of each product is not necessarily performed by NVIDIA. It is customer’s sole responsibility to ensure the product is suitable and fit for the application planned by customer and to do the necessary testing for the application in order to avoid a default of the application or the product. Weaknesses in customer’s product designs may affect the quality and reliability of the NVIDIA product and may result in additional or different conditions and/or requirements beyond those contained in this guide. NVIDIA does not accept any liability related to any default, damage, costs or problem which may be based on or attributable to: (i) the use of the NVIDIA product in any manner that is contrary to this guide, or (ii) customer product designs.}
_{Other than the right for customer to use the information in this guide with the product, no other license, either expressed or implied, is hereby granted by NVIDIA under this guide. Reproduction of information in this guide is permissible only if reproduction is approved by NVIDIA in writing, is reproduced without alteration, and is accompanied by all associated conditions, limitations, and notices.}
Trademarks
_{NVIDIA, the NVIDIA logo, and cuBLAS, CUDA, cuDNN, DALI, DIGITS, DGX, DGX1, DGX2, DGX Station, DLProf, Jetson, Kepler, Maxwell, NCCL, Nsight Compute, Nsight Systems, NvCaffe, PerfWorks, Pascal, SDK Manager, Tegra, TensorRT, TensorRT Inference Server, Tesla, TFTRT, and Volta are trademarks and/or registered trademarks of NVIDIA Corporation in the United States and other countries. Other company and product names may be trademarks of the respective companies with which they are associated.}