ccp.h

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/*
 * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef CCP_H
#define CCP_H
#include <stdint.h>

typedef enum
{
    NVCCP_STATUS_OK = 0,
    NVCCP_STATUS_DENIED,
    NVCCP_STATUS_NOT_REGISTERED,
    NVCCP_STATUS_ALREADY_ON,
    NVCCP_STATUS_ALREADY_OFF,
    NVCCP_STATUS_SLAVE_RUNNING,
    NVCCP_STATUS_I2C_OWNERSHIP_DENIED,
    NVCCP_REQ_FILE_OP_FAIL = 1000,
    NVCCP_REQ_TIMEOUT,
    NVCCP_REQ_INVALID,
    NVCCP_REQ_DENIED,
    NVCCP_REQ_FAILED,
    NVCCP_REQ_CONNECT_ERR,
} nvccp_return_t;


typedef enum {
    NVCCP_GROUP_A = 0x00,
    NVCCP_GROUP_B = 0x01,
    NVCCP_GROUP_C = 0x02,
    NVCCP_GROUP_D = 0x03
} nvccp_cam_group_id;

typedef enum{
    /* Camera group A */
    NVCCP_CAM_A0 = 0x01,
    NVCCP_CAM_A1 = 0x02,
    NVCCP_CAM_A2 = 0x04,
    NVCCP_CAM_A3 = 0x08,
    /* Camera group B */
    NVCCP_CAM_B0 = 0x10,
    NVCCP_CAM_B1 = 0x20,
    NVCCP_CAM_B2 = 0x40,
    NVCCP_CAM_B3 = 0x80,
    /* Camera group C */
    NVCCP_CAM_C0 = 0x0100,
    NVCCP_CAM_C1 = 0x0200,
    NVCCP_CAM_C2 = 0x0400,
    NVCCP_CAM_C3 = 0x0800,
    /* Camera group D */
    NVCCP_CAM_D0 = 0x1000,
    NVCCP_CAM_D1 = 0x2000,
    NVCCP_CAM_D2 = 0x4000,
    NVCCP_CAM_D3 = 0x8000
} nvccp_cam_id;

typedef enum {
    NVCCP_TEGRA_A = 0x41,
    NVCCP_TEGRA_B = 0x42,
    NVCCP_TEGRA_C = 0x43
} nvccp_tegra_id;

typedef enum {
    NVCCP_CAM_MASTER = 0x01,
    NVCCP_CAM_SLAVE
} nvccp_cam_mode;

nvccp_return_t nvccp_request_ownership(nvccp_cam_group_id cam_group,nvccp_cam_mode cam_master);

nvccp_return_t nvccp_release_ownership(nvccp_cam_group_id cam_group,nvccp_cam_mode cam_master);

nvccp_return_t nvccp_set_cam_pwr_on(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_set_cam_pwr_off(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_set_cam_unit_pwr_on(nvccp_cam_id cam_id);

nvccp_return_t nvccp_set_cam_unit_pwr_off(nvccp_cam_id cam_id);

nvccp_return_t nvccp_set_aggreg_pwr_on(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_set_aggreg_pwr_off(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_set_frsync_owner(nvccp_tegra_id tegra_id);

nvccp_return_t nvccp_set_frsync_enable(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_set_frsync_disable(nvccp_cam_group_id cam_group);

nvccp_return_t nvccp_get_cam_unit_pwr_status(uint16_t *cam_id);

nvccp_return_t nvccp_get_aggreg_pwr_status(uint8_t *cam_group);

nvccp_return_t nvccp_get_frsync_enable_status(uint8_t *cam_group);
#endif