NVIDIA DRIVE OS Linux API Reference

5.1.3.0 Release

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QbSdmmcDriverPrivInfo Struct Reference

Detailed Description

Holds the context structure for the SDMMC driver.

A pointer to this structure is passed into the driver's Init() routine. This pointer is the only data that can be kept in a global variable for later reference.

Definition at line 222 of file sdmmc.h.

Collaboration diagram for QbSdmmcDriverPrivInfo:

Data Fields

NvBool IsEsd
 Defines whether the driver is for an ESD card (vs eMMC). More...
 
NvU8 BlockSizeLog2
 Holds the block size. More...
 
NvU8 PageSizeLog2
 Holds the page size. More...
 
NvU8 PagesPerBlockLog2
 Holds the number of pages per block. More...
 
NvU32 CardRca
 Holds the card's Relative Card Address. More...
 
NvU32 SdmmcResponse [NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES/sizeof(NvU32)]
 Holds a response buffer. More...
 
QbDeviceStatus DeviceStatus
 Holds the device status. More...
 
NvU32 XferStartTime
 Holds the Movi Nand Read/Write start time. More...
 
NvBool HighSpeedMode
 Defines whether to access the card in high speed mode. More...
 
NvBool EnhancedStrobeMode
 Defines whether to access the card in HS400 ESM. More...
 
NvBool IsHighCapacityCard
 Defines whether the card is a high capacity card. More...
 
NvU8 SpecVersion
 Holds the spec version. More...
 
NvU8 ExtCsdSpecVersion
 Holds the ExtCsdSpecVersion. More...
 
NvU32 EmmcBootPartitionSize
 Holds Emmc Boot Partition size. More...
 
SdmmcAccessRegion CurrentAccessRegion
 Holds the current access region. More...
 
NvBootSdmmcCardClock CurrentClockRate
 Holds the current clock rate. More...
 
NvU8 SdmmcInternalBuffer [NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES]
 Defines a buffer for selecting high speed, reading extended CSD and SCR. More...
 
NvU8 taac
 Defines read access time1. More...
 
NvU8 nsac
 Defines read access time2. More...
 
NvU8 TranSpeed
 Defines the clock frequency when not in high speed mode. More...
 
NvU8 TranSpeedInMHz
 Defines the transfer speed in MHz. More...
 
NvBool HostSupportsHighSpeedMode
 Defines whether the host supports high speed mode. More...
 
NvBool CardSupportsHighSpeedMode
 Defines whether the card supports high speed mode. More...
 
NvU8 PageSizeLog2ForCapacity
 Holds the page size to use for card capacity calculation. More...
 
NvU8 PowerClass26MHz360V
 Holds the power class for 26MHz at 3.6V. More...
 
NvU8 PowerClass52MHz360V
 Holds the power class for 52MHz at 3.6V. More...
 
NvU8 PowerClass26MHz195V
 Holds the power class for 26MHz at 1.95V. More...
 
NvU8 PowerClass52MHz195V
 Holds the power class for 52MHz at 1.95V. More...
 
NvU8 BootConfig
 Holds the boot config from ExtCSD. More...
 
NvBool IsHighVoltageRange
 Defines whether high voltage range is used for card identification. More...
 
NvU8 MaxPowerClassSupported
 Holds the Max Power class supported by target board. More...
 
NvU32 NumOfBlocks
 Holds the number of blocks present in card. More...
 
NvU32 XferTimeOutInUs
 Holds read/write time out at current card clock frequency. More...
 
NvU8 SdmmcBootModeBuffer [NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES]
 Holds data read in boot mode. More...
 
NvBool BootModeReadInProgress
 Defines whether you are reading in boot mode. More...
 
NvU8 CardSupportSpeed
 Flag to indicate the card speed and operating voltage level. More...
 
NvU8 PowerClass52MHzDdr360V
 Power class for 52 Mhz DDR @ 3.6V. More...
 
NvU8 PowerClass52MHzDdr195V
 Power class for 52 Mhz DDR @ 1.95V. More...
 
NvU8 PowerClass200MHzDdr180V
 Power class for 200 Mhz DDR @ 3.6V. More...
 
NvU8 IsDdrMode
 Indicates whether Ddr mode is used for data transfer. More...
 
NvBool IsPLLP
 Indicates whether Parent clock source is PLLP or PLLC4. More...
 
NvU32 RegPhyBase
 
NvU32 RegLen
 
NvU32 RegVirtBase
 
QbSdmmcInfopdata
 
NvU32 VendorClockCtrl
 
SdmmcInitLevel SdmmcInitType
 
NvBool DisableHS400
 
NvBool IsCardReady
 
NvBool Support64BitDmaAddr
 

Field Documentation

NvU8 QbSdmmcDriverPrivInfo::BlockSizeLog2

Holds the block size.

Definition at line 227 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::BootConfig

Holds the boot config from ExtCSD.

Definition at line 283 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::BootModeReadInProgress

Defines whether you are reading in boot mode.

Definition at line 295 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::CardRca

Holds the card's Relative Card Address.

Definition at line 233 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::CardSupportsHighSpeedMode

Defines whether the card supports high speed mode.

Definition at line 271 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::CardSupportSpeed

Flag to indicate the card speed and operating voltage level.

Definition at line 297 of file sdmmc.h.

SdmmcAccessRegion QbSdmmcDriverPrivInfo::CurrentAccessRegion

Holds the current access region.

Definition at line 255 of file sdmmc.h.

NvBootSdmmcCardClock QbSdmmcDriverPrivInfo::CurrentClockRate

Holds the current clock rate.

Definition at line 257 of file sdmmc.h.

QbDeviceStatus QbSdmmcDriverPrivInfo::DeviceStatus

Holds the device status.

Definition at line 239 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::DisableHS400

Definition at line 316 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::EmmcBootPartitionSize

Holds Emmc Boot Partition size.

Definition at line 253 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::EnhancedStrobeMode

Defines whether to access the card in HS400 ESM.

Definition at line 245 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::ExtCsdSpecVersion

Holds the ExtCsdSpecVersion.

Definition at line 251 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::HighSpeedMode

Defines whether to access the card in high speed mode.

Definition at line 243 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::HostSupportsHighSpeedMode

Defines whether the host supports high speed mode.

Definition at line 269 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::IsCardReady

Definition at line 318 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::IsDdrMode

Indicates whether Ddr mode is used for data transfer.

Definition at line 305 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::IsEsd

Defines whether the driver is for an ESD card (vs eMMC).

Definition at line 225 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::IsHighCapacityCard

Defines whether the card is a high capacity card.

Definition at line 247 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::IsHighVoltageRange

Defines whether high voltage range is used for card identification.

Definition at line 285 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::IsPLLP

Indicates whether Parent clock source is PLLP or PLLC4.

Definition at line 307 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::MaxPowerClassSupported

Holds the Max Power class supported by target board.

Definition at line 287 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::nsac

Defines read access time2.

Definition at line 263 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::NumOfBlocks

Holds the number of blocks present in card.

Definition at line 289 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PageSizeLog2

Holds the page size.

Definition at line 229 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PageSizeLog2ForCapacity

Holds the page size to use for card capacity calculation.

Definition at line 273 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PagesPerBlockLog2

Holds the number of pages per block.

Definition at line 231 of file sdmmc.h.

QbSdmmcInfo* QbSdmmcDriverPrivInfo::pdata

Definition at line 312 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass200MHzDdr180V

Power class for 200 Mhz DDR @ 3.6V.

Definition at line 303 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass26MHz195V

Holds the power class for 26MHz at 1.95V.

Definition at line 279 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass26MHz360V

Holds the power class for 26MHz at 3.6V.

Definition at line 275 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass52MHz195V

Holds the power class for 52MHz at 1.95V.

Definition at line 281 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass52MHz360V

Holds the power class for 52MHz at 3.6V.

Definition at line 277 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass52MHzDdr195V

Power class for 52 Mhz DDR @ 1.95V.

Definition at line 301 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::PowerClass52MHzDdr360V

Power class for 52 Mhz DDR @ 3.6V.

Definition at line 299 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::RegLen

Definition at line 310 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::RegPhyBase

Definition at line 309 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::RegVirtBase

Definition at line 311 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::SdmmcBootModeBuffer[NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES]

Holds data read in boot mode.

Definition at line 293 of file sdmmc.h.

SdmmcInitLevel QbSdmmcDriverPrivInfo::SdmmcInitType

Definition at line 314 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::SdmmcInternalBuffer[NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES]

Defines a buffer for selecting high speed, reading extended CSD and SCR.

Definition at line 259 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::SdmmcResponse[NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES/sizeof(NvU32)]

Holds a response buffer.

To make it word aligned, the value for this field must be defined as NvU32.

Definition at line 237 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::SpecVersion

Holds the spec version.

Definition at line 249 of file sdmmc.h.

NvBool QbSdmmcDriverPrivInfo::Support64BitDmaAddr

Definition at line 319 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::taac

Defines read access time1.

Definition at line 261 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::TranSpeed

Defines the clock frequency when not in high speed mode.

Definition at line 265 of file sdmmc.h.

NvU8 QbSdmmcDriverPrivInfo::TranSpeedInMHz

Defines the transfer speed in MHz.

Definition at line 267 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::VendorClockCtrl

Definition at line 313 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::XferStartTime

Holds the Movi Nand Read/Write start time.

Definition at line 241 of file sdmmc.h.

NvU32 QbSdmmcDriverPrivInfo::XferTimeOutInUs

Holds read/write time out at current card clock frequency.

Definition at line 291 of file sdmmc.h.


The documentation for this struct was generated from the following file: