NVIDIA DRIVE OS Linux API Reference

5.1.3.0 Release

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QspiControllerData Struct Reference

Detailed Description

Holds QSPI hardware controller context data.

Definition at line 129 of file qspi.h.

Collaboration diagram for QspiControllerData:

Data Fields

NvU32 Instance
 QSPI hardware controller instance. More...
 
NvU32 BaseAddr
 QSPI hardware register base address. More...
 
QspiOpMode_t OpMode
 DDR or SDR mode taken from the DT/ board file. More...
 
NvU32 DmaChannel
 GPCDMA channel number if DMA is enabled for QSPI IO. More...
 
NvU32 DmaClient
 Time at which the read xfer is started. More...
 
NvU32 ReadStartTimeinUs
 Time at which the read xfer is started. More...
 
NvU32 WriteStartTimeinUs
 Time at which the write xfer is started. More...
 
NvU32 ChipSelectLevel
 CS assert level, Active Low or Active High. More...
 
NvU32 CSActiveBwPkts
 For software type CS, 1 enables the CS. More...
 
NvU32 CyclesBwPkts
 Idle clock cycles between two packets. More...
 
NvU32 TxClkTapDelay
 Tx TAP delay for sampling data. More...
 
NvU32 RxClkTapDelay
 Rx TAP delay for sampling data. More...
 
NvU32 QuadState
 Quad state. More...
 
QspiTransfer Transfers [3]
 Message, which consists of 3 transfers: <CMD><Address><Data>. More...
 

Field Documentation

NvU32 QspiControllerData::BaseAddr

QSPI hardware register base address.

Definition at line 132 of file qspi.h.

NvU32 QspiControllerData::ChipSelectLevel

CS assert level, Active Low or Active High.

The value is specified in the DT / board file.

Definition at line 145 of file qspi.h.

NvU32 QspiControllerData::CSActiveBwPkts

For software type CS, 1 enables the CS.

0 disables it, between packets.

Definition at line 148 of file qspi.h.

NvU32 QspiControllerData::CyclesBwPkts

Idle clock cycles between two packets.

Definition at line 149 of file qspi.h.

NvU32 QspiControllerData::DmaChannel

GPCDMA channel number if DMA is enabled for QSPI IO.

Definition at line 138 of file qspi.h.

NvU32 QspiControllerData::DmaClient

Time at which the read xfer is started.

Definition at line 139 of file qspi.h.

NvU32 QspiControllerData::Instance

QSPI hardware controller instance.

Definition at line 131 of file qspi.h.

QspiOpMode_t QspiControllerData::OpMode

DDR or SDR mode taken from the DT/ board file.

If set to DDR, the mode is enabled for ADDRESS & DATA transfer. If set to SDR, all the transfers will be SDR only.

Definition at line 137 of file qspi.h.

NvU32 QspiControllerData::QuadState

Quad state.

Definition at line 152 of file qspi.h.

NvU32 QspiControllerData::ReadStartTimeinUs

Time at which the read xfer is started.

Definition at line 140 of file qspi.h.

NvU32 QspiControllerData::RxClkTapDelay

Rx TAP delay for sampling data.

Definition at line 151 of file qspi.h.

QspiTransfer QspiControllerData::Transfers[3]

Message, which consists of 3 transfers: <CMD><Address><Data>.

Definition at line 155 of file qspi.h.

NvU32 QspiControllerData::TxClkTapDelay

Tx TAP delay for sampling data.

Definition at line 150 of file qspi.h.

NvU32 QspiControllerData::WriteStartTimeinUs

Time at which the write xfer is started.

Definition at line 141 of file qspi.h.


The documentation for this struct was generated from the following file: