NVIDIA DRIVE OS Linux API Reference

5.1.3.0 Release

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QspiTransfer Struct Reference

Detailed Description

Holds QSPI Transfer data.

The message consists of multiple transfers.

Definition at line 114 of file qspi.h.

Data Fields

NvU8 * Txbuf
 TX buffer address. More...
 
NvU8 * Rxbuf
 RX buffer address. More...
 
NvU32 Mode
 QSPI X1 or X2 or X4 xfer mode. More...
 
NvU32 Writelen
 TX length. More...
 
NvU32 Readlen
 RX length. More...
 
NvU32 Speed_hz
 QSPI clock frequency. More...
 
NvU32 BusWidth
 QSPI controller FIFO width. More...
 
NvU32 DummyCycles
 Clock cycles between two transaction. More...
 
QspiXferType_t type
 ASYNC or SYNC xfer. More...
 
QspiOpMode_t OpMode
 DDR or SDR mode of xfer. More...
 

Field Documentation

NvU32 QspiTransfer::BusWidth

QSPI controller FIFO width.

Definition at line 122 of file qspi.h.

NvU32 QspiTransfer::DummyCycles

Clock cycles between two transaction.

Definition at line 123 of file qspi.h.

NvU32 QspiTransfer::Mode

QSPI X1 or X2 or X4 xfer mode.

Definition at line 118 of file qspi.h.

QspiOpMode_t QspiTransfer::OpMode

DDR or SDR mode of xfer.

Definition at line 125 of file qspi.h.

NvU32 QspiTransfer::Readlen

RX length.

Definition at line 120 of file qspi.h.

NvU8* QspiTransfer::Rxbuf

RX buffer address.

Definition at line 117 of file qspi.h.

NvU32 QspiTransfer::Speed_hz

QSPI clock frequency.

Definition at line 121 of file qspi.h.

NvU8* QspiTransfer::Txbuf

TX buffer address.

Definition at line 116 of file qspi.h.

QspiXferType_t QspiTransfer::type

ASYNC or SYNC xfer.

Definition at line 124 of file qspi.h.

NvU32 QspiTransfer::Writelen

TX length.

Definition at line 119 of file qspi.h.


The documentation for this struct was generated from the following file: