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5.1.3.0 Release

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gpc_dma.h
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1 /*
2  * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3  *
4  * NVIDIA CORPORATION and its licensors retain all intellectual property
5  * and proprietary rights in and to this software, related documentation
6  * and any modifications thereto. Any use, reproduction, disclosure or
7  * distribution of this software and related documentation without an express
8  * license agreement from NVIDIA CORPORATION is strictly prohibited.
9  */
10 
19 #ifndef INCLUDED_GPCDMA_H
20 #define INCLUDED_GPCDMA_H
21 
29 #include <nvcommon.h>
30 #include <dma_common.h>
31 
33 //#define QB_GPCDMA_DEBUG 1
34 
35 #ifdef QB_GPCDMA_DEBUG
36 #define QB_GPCDMA_DBG(fmt, args...) pr_info(fmt, ##args)
37 #else
38 #define QB_GPCDMA_DBG(fmt, args...)
39 #endif
40 
42 #define MAX_GPCDMA_CONTROLLERS 1
43 #define GPCDMA_MC_OUTSTANDING_REQS 16
45 #define GPCDMA_TRIG_SEL_OFFSET 9
48 #define MIN_GPCDMA_TRIG_SEL (CHANNEL_0+GPCDMA_TRIG_SEL_OFFSET)
50 #define MAX_GPCDMA_TRIG_SEL (CHANNEL_31+GPCDMA_TRIG_SEL_OFFSET)
52 
56 typedef enum
57 {
64 #ifdef CONFIG_T19x
65  GPCDMA_CLIENT6_QSPI1,
66 #else
68 #endif
94 } ApbSlave;
95 
96 
100 typedef enum
101 {
136 } GpcDmaChannel;
137 
141 typedef enum
142 {
159 } XferMode;
160 
165 typedef enum
166 {
183 typedef struct
184 {
188  NvU64 SrcAddrPhy;
190  NvU64 DestAddrPhy;
192  NvU32 XferSize;
199 
203  NvU32 TrigSel;
211 typedef struct
212 {
218 
227 NvError QbGpcdmaInit(void);
228 
229 
232 #endif /* #ifndef INCLUDED_NVTBOOT_GPCDMA_H */
Specifies DMA from Memory to Memory.
Definition: gpc_dma.h:152
GpcDmaChStatus Status
Specifies the DMA channel status.
Definition: gpc_dma.h:216
NvU64 DestAddrPhy
Specifies the Physical address of Dest. memory (MC addr or FIFO base)
Definition: gpc_dma.h:190
NvU32 XferSize
Specifies Transfer size in bytes.
Definition: gpc_dma.h:192
NvU32 TrigSel
Specifies Trigger for the DMA to start in this channel Note : At present only Channels can be used as...
Definition: gpc_dma.h:203
Specifies DMA Done channel state.
Definition: gpc_dma.h:175
Defines the GPCDMA Channel Context.
Definition: gpc_dma.h:183
Specifies UNDEFINED channel state, this is the state when no DMA is initiated in the channel...
Definition: gpc_dma.h:169
Specifies DMA from Memory to IO Device with flow control.
Definition: gpc_dma.h:150
Specifies DMA from IO Device to Memory with flow control.
Definition: gpc_dma.h:146
Specifies Maximum value for channel state Channel state should never be read as this value...
Definition: gpc_dma.h:178
NvError
The NvError enumeration contains ALL return / error codes.
Definition: nverror.h:36
XferMode mode
Specifies DMA Transfer mode.
Definition: gpc_dma.h:194
GpcDmaChannel
Defines the GPCDMA channels.
Definition: gpc_dma.h:100
GpcDmaChStatus
Defines the GPCDMA State of Transfer.
Definition: gpc_dma.h:165
NvError QbGpcdmaInit(void)
GPCDMA driver initialization function called during QB initialization.
Specifies Maximum value for DMA mode.
Definition: gpc_dma.h:158
ApbSlave ApbSlaveID
Specifies IO device involved in DMA.
Definition: gpc_dma.h:196
Specifies DMA pending channel state.
Definition: gpc_dma.h:171
ApbSlave
Defines the GPCDMA clients.
Definition: gpc_dma.h:56
Specifies Reserved DMA mode.
Definition: gpc_dma.h:154
Specifies DMA in progress channel state.
Definition: gpc_dma.h:173
XferMode
Defines the GPCDMA Mode of Transfer.
Definition: gpc_dma.h:141
NvU64 SrcAddrPhy
Specifies the Physical address of source memory (MC addr or FIFO base)
Definition: gpc_dma.h:188
Specifies DMA from Memory to IO Device with no flow control.
Definition: gpc_dma.h:148
GpcDmaChannel Ch
Specifies the GPCDMA channel used.
Definition: gpc_dma.h:186
NvU32 FixedPattern
Specifies the Fixed Pattern to be DMAed to memory.
Definition: gpc_dma.h:198
Specifies Fixed Pattern DMA mode.
Definition: gpc_dma.h:156
Specifies DMA from IO Device to Memory with no flow control.
Definition: gpc_dma.h:144
Defines the GPCDMA Channel Status Context.
Definition: gpc_dma.h:211
GpcDmaChannel Ch
Specifies the DMA channel for which the status is queried.
Definition: gpc_dma.h:214