NVIDIA DRIVE OS Linux API Reference

5.1.3.0 Release

 All Data Structures Namespaces Files Functions Variables Typedefs Enumerations Enumerator Macros Groups Pages
qspi.h
Go to the documentation of this file.
1 /*
2  * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3  *
4  * NVIDIA CORPORATION and its licensors retain all intellectual property
5  * and proprietary rights in and to this software, related documentation
6  * and any modifications thereto. Any use, reproduction, disclosure or
7  * distribution of this software and related documentation without an express
8  * license agreement from NVIDIA CORPORATION is strictly prohibited.
9  */
10 
18 #ifndef _QB_QSPI_H_
19 #define _QB_QSPI_H_
20 
29 #include <device.h>
30 #include <nvcommon.h>
31 #include <nverror.h>
32 
33 // Enable this to print debug messages.
34 // #define DEBUG_QSPI 1
35 
36 #define DEBUG_QSPI 0
37 #if DEBUG_QSPI
38 #define PRINT_QSPI_DBG_MESSAGES(...) pr_info(__VA_ARGS__)
39 #define PRINT_QSPI_REG_ACCESS(...) pr_info(__VA_ARGS__)
40 #else
41 #define PRINT_QSPI_DBG_MESSAGES(...)
42 #define PRINT_QSPI_REG_ACCESS(...)
43 #endif
44 
45 #ifdef CONFIG_T19x
46 #define QSPI_CONTROLLERS_MAX 2
47 #else
48 #define QSPI_CONTROLLERS_MAX 1
49 #endif
50 
56 };
57 
58 #define QSPI_MAX_BIT_LENGTH 31
59 #define QSPI_8Bit_BIT_LENGTH 7
60 #define QSPI_FIFO_DEPTH 64
61 #define BYTES_PER_WORD 4
62 
64 #define QSPI_HW_TIMEOUT 100000
65 
66 /* Flush fifo timeout, resolution = 10us */
67 #define FLUSHFIFO_TIMEOUT 10000 /* 10000 x 10us = 100ms */
68 
69 /* Max QSPI transfer in term of words */
70 #ifdef CONFIG_T186
71 #define MAX_QSPI_XFERSIZE 65536
72 #else
73 #define MAX_QSPI_XFERSIZE (256 * MB)
74 #endif
75 
76 // Wrapper macros for reading/writing from/to QSPI
77 #define QSPI_REG_READ32(reg, Instance) \
78  NV_READ32(pg_QspiContext[Instance]->BaseAddr + (QSPI_##reg##_0))
79 
80 #define QSPI_REG_WRITE32(reg, val, Instance) \
81  NV_WRITE32((pg_QspiContext[Instance]->BaseAddr + (QSPI_##reg##_0)), (val))
82 
83 
84 #define QSPI_REG_WRITE32_FLUSH(reg, val, Instance) \
85 { \
86  NV_WRITE32_FENCE((pg_QspiContext[Instance]->BaseAddr + \
87  (QSPI_##reg##_0)), (val)); \
88 }
89 
91 typedef enum
92 {
96 
98 typedef enum
99 {
103 
104 
106 typedef enum {
107  SDR_MODE = 0,
109 } QspiOpMode_t;
110 
114 typedef struct QspiTransfer
115 {
116  NvU8 *Txbuf;
117  NvU8 *Rxbuf;
118  NvU32 Mode;
119  NvU32 Writelen;
120  NvU32 Readlen;
121  NvU32 Speed_hz;
122  NvU32 BusWidth;
123  NvU32 DummyCycles;
126 } QspiTransfer;
127 
129 typedef struct
130 {
131  NvU32 Instance;
132  NvU32 BaseAddr;
133 
138  NvU32 DmaChannel;
139  NvU32 DmaClient;
142 
146 
149  NvU32 CyclesBwPkts;
152  NvU32 QuadState;
153 
155  QspiTransfer Transfers[3];
157 
159 
167 NvError NvQspiInit(void *pdata);
168 
177 NvError
178 QspiHwProcReadAsyncWaitDMAComplete(NvU32 Instance);
179 
191 NvError
193  QspiTransfer *Transfers,
194  NvU8 Numoftransfers,
195  NvU32 Instance);
196 
197 #endif /* _QB_QSPI_H_ */
198 
NvU32 QuadState
Quad state.
Definition: qspi.h:152
QspiOpMode_t OpMode
DDR or SDR mode taken from the DT/ board file.
Definition: qspi.h:137
NvU32 Mode
QSPI X1 or X2 or X4 xfer mode.
Definition: qspi.h:118
=0
Definition: qspi.h:100
=1
Definition: qspi.h:101
QspiControllerData * pg_QspiContext[QSPI_CONTROLLERS_MAX]
NvU32 ChipSelectLevel
CS assert level, Active Low or Active High.
Definition: qspi.h:145
Holds QSPI Transfer data.
Definition: qspi.h:114
NvError NvQspiTransaction(QspiTransfer *Transfers, NvU8 Numoftransfers, NvU32 Instance)
Performs QSPI transactions for write and read.
struct QspiTransfer QspiTransfer
Holds QSPI Transfer data.
NvU32 Instance
QSPI hardware controller instance.
Definition: qspi.h:131
NvU8 * Txbuf
TX buffer address.
Definition: qspi.h:116
Holds QSPI hardware controller context data.
Definition: qspi.h:129
NvError
The NvError enumeration contains ALL return / error codes.
Definition: nverror.h:36
NvU8 * Rxbuf
RX buffer address.
Definition: qspi.h:117
NvU32 CyclesBwPkts
Idle clock cycles between two packets.
Definition: qspi.h:149
QspiOpMode_t OpMode
DDR or SDR mode of xfer.
Definition: qspi.h:125
NvU32 ReadStartTimeinUs
Time at which the read xfer is started.
Definition: qspi.h:140
1 [IO on rising and falling edge of clock]
Definition: qspi.h:108
QspiXferType_t
Defines the transfer types.
Definition: qspi.h:98
QspiBusWidth
Defines the QSPI bus widths.
Definition: qspi.h:52
#define QSPI_CONTROLLERS_MAX
Definition: qspi.h:48
QspiOpMode_t
Defines the QSPI controller and Flash chip operating mode.
Definition: qspi.h:106
NvU32 CSActiveBwPkts
For software type CS, 1 enables the CS.
Definition: qspi.h:148
NvU32 BaseAddr
QSPI hardware register base address.
Definition: qspi.h:132
NvU32 BusWidth
QSPI controller FIFO width.
Definition: qspi.h:122
NVIDIA Quickboot Interface: Error Handling (Parker)
NvU32 RxClkTapDelay
Rx TAP delay for sampling data.
Definition: qspi.h:151
NvU32 Writelen
TX length.
Definition: qspi.h:119
NvU32 DummyCycles
Clock cycles between two transaction.
Definition: qspi.h:123
NvU32 DmaClient
Time at which the read xfer is started.
Definition: qspi.h:139
NvU32 WriteStartTimeinUs
Time at which the write xfer is started.
Definition: qspi.h:141
0 [IO on single edge of clock]
Definition: qspi.h:107
NvU32 Speed_hz
QSPI clock frequency.
Definition: qspi.h:121
NVIDIA Quickboot Interface: Device Drivers
NvU32 DmaChannel
GPCDMA channel number if DMA is enabled for QSPI IO.
Definition: qspi.h:138
QspiXferType_t type
ASYNC or SYNC xfer.
Definition: qspi.h:124
NvQspiChipSelect
Defines the QSPI chip selection.
Definition: qspi.h:91
NvU32 TxClkTapDelay
Tx TAP delay for sampling data.
Definition: qspi.h:150
NvError NvQspiInit(void *pdata)
Initializes the specified QSPI controller.
NvU32 Readlen
RX length.
Definition: qspi.h:120
NvError QspiHwProcReadAsyncWaitDMAComplete(NvU32 Instance)
Waits until the IO from the DMA is complete.