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qspi_flash.h
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1 /*
2  * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
3  *
4  * NVIDIA CORPORATION and its licensors retain all intellectual property
5  * and proprietary rights in and to this software, related documentation
6  * and any modifications thereto. Any use, reproduction, disclosure or
7  * distribution of this software and related documentation without an express
8  * license agreement from NVIDIA CORPORATION is strictly prohibited.
9  */
10 
18 #ifndef INCLUDED_QSPI_FLASH_H
19 #define INCLUDED_QSPI_FLASH_H
20 
21 #include <device.h>
30 #include <nvcommon.h>
31 #include <nverror.h>
32 #include <qspi.h>
33 
35 #ifdef CONFIG_T19x
36 #define QSPI_FLASH_MAX_INSTANCES 2
37 #else
38 #define QSPI_FLASH_MAX_INSTANCES 1
39 #endif
40 
42 #define QSPI_READ_ASYNC_PAGE_SIZE (256 * KB)
43 
47 #define QSPI_READ_ASYNC_PAGE_SIZE_LZF (256 * KB)
48 
50 #define QSPI_FLASH_CMD_REMS 0x90U
51 #define QSPI_FLASH_CMD_RDID 0x9FU
52 #define QSPI_FLASH_CMD_RES 0xABU
53 #define QSPI_FLASH_CMD_RSFDP 0x5AU
54 
55 #define QSPIFLASH_DDR_QUAD_READ_COMMAND 0xeeU
56 #define QSPIFLASH_SDR_QUAD_READ_COMMAND 0xecU
57 #define QSPI_FLASH_WRITE_COMMAND 0x12U
58 #define QSPI_FLASH_SECTOR_ERASE_COMMAND 0xDCU
59 #define QSPI_FLASH_SUB_SECTOR_ERASE_COMMAND 0x21U
60 
61 #define QSPI_FLASH_QUAD_ENABLE 0x02
62 #define QSPI_FLASH_QUAD_DISABLE 0x0
63 #define QSPI_FLASH_WEL_ENABLE 0x02
64 #define QSPI_FLASH_WEL_DISABLE 0x00
65 #define QSPI_FLASH_PROGRAM_ERR (1 << 6)
66 #define QSPI_FLASH_ERASE_ERR (1 << 5)
67 #define QSPI_FLASH_WIP_ENABLE 0x01
68 #define QSPI_FLASH_WIP_ENABLE 0x01
69 #define QSPI_FLASH_WIP_WAIT_TIME 1000
70 
71 #define QSPI_FLASH_CMD_RDSR1 0x5
72 #define QSPI_FLASH_CMD_RDCR 0x35
73 #define QSPI_FLASH_CMD_MODE_RESET 0xFF
74 #define QSPI_FLASH_CMD_WRR 0x1
75 #define QSPI_FLASH_CMD_WRAR 0x71
76 #define QSPI_FLASH_CMD_CLEAR_STATUS 0x82
77 #define QSPI_FLASH_CMD_WRITE_ENABLE 0x06
78 #define QSPI_FLASH_CMD_WRITE_DISABLE 0x04
79 #define QSPI_FLASH_CMD_WRAR_CR1V 0x800002
80 
81 #define QSPI_DEFAULT_DUMMY_CYCLES 0
82 
83 #define QSPI_FLASH_NUM_OF_TRANSFERS 3
84 #define QSPI_FLASH_COMMAND_WIDTH 1
85 #define QSPI_FLASH_ADDRESS_WIDTH 4
86 #define QSPI_FLASH_QSPI_FLASH_DATA_TRANSFER 2
87 #ifdef CONFIG_T186
88 #define QSPI_FLASH_MAX_TRANSFER_SIZE(_a) (65536 * 4)
89 #else
90 #define QSPI_FLASH_MAX_TRANSFER_SIZE(_a) QSPI_FLASH_SIZE(_a)
91 #endif
92 #define QSPI_FLASH_CMD_MODE_VAL 0x0
93 #define QSPI_FLASH_ADDR_DATA_MODE_VAL 0x0
94 #define QSPI_FLASH_CLEAR_STATUS_WAIT_TIME 100
95 #define QSPI_FLASH_WRITE_ENABLE_WAIT_TIME 100
96 #define QSPI_FLASH_WE_RETRY_COUNT 100
97 
98 #define PAGE_WRITE_SIZE 256
99 
101 #define MANUFACTURE_ID_SPANSION 0x01U
102 #define MANUFACTURE_ID_WINBOND 0xEFU
103 #define MANUFACTURE_ID_MICRON 0x20U
104 #define MANUFACTURE_ID_MACRONIX 0xC2U
105 #define DEVICE_ID_LEN 3U
106 
108 #define FLAG_PAGE512 0x01U
109 #define FLAG_QPI 0x02U
110 #define FLAG_QUAD 0x04U
111 #define FLAG_BULK 0x08U
112 #define FLAG_PAGE_SIZE_512 0x10U
113 #define FLAG_DDR 0x20U
114 #define FLAG_UNIFORM 0x40U
115 #define FLAG_PAGE512_FIXED 0x80U
116 
118 #define QSPI_FLASH_SIZE(_a) \
119  ((1 << (_a)->pFlashInfo->SectorSize) * (1 << (_a)->pFlashInfo->SectorCnt))
120 #define QSPI_FLASH_SECTOR_SIZE(_a) (1 << (_a)->pFlashInfo->SectorSize)
121 #define QSPI_FLASH_SECTORS(_a) (1 << (_a)->pFlashInfo->SectorCnt)
122 #define QSPI_FLASH_SUB_SECTOR_SIZE(_a) (1 << (_a)->pFlashInfo->SubSectorSize)
123 #define QSPI_FLASH_SUB_SECTORS(_a) ((_a)->pFlashInfo->SubSectorCnt)
124 #define QSPI_FLASH_SUB_SECTOR_LOC 0
125 
130 typedef enum
131 {
135 
139 typedef struct QspiAsyncIOStatus
140 {
143 
145  NvU32 Offset;
146  void *Buffer;
148 
152 typedef struct QspiFlashInfo
153 {
155  NvS8 FlashName[32];
156 
159 
161  NvU8 MemType;
162 
164  NvU8 Density;
165 
168 
170  NvU8 SectorCnt;
171 
174 
177 
179  NvU8 Flag;
181 
185 typedef struct QspiFlashDevice
186 {
188  NvU32 Instance;
189 
192 
196 
199 
202 
206 
207 extern struct QspiFlashInfo QbFlashInfoList[];
209 
214 NvError QbQspiInit(void);
215 
216 #endif /* INCLUDED_QSPI_FLASH_H */
217 
NvU8 MemType
MemType: Memory Type of the flash.
Definition: qspi_flash.h:161
NvU8 Flag
Flag: support feature of the flash (DDR, QPI, BULK)
Definition: qspi_flash.h:179
NvU8 ManufactureID
ManufactureID: Manufacture ID of the flash.
Definition: qspi_flash.h:158
QspiXferStatus_t
Defines the QSPI Transfer status, where completed = 0.
Definition: qspi_flash.h:130
NvU8 SectorCnt
SectorCnt: Number of sectors of the flash (power of 2)
Definition: qspi_flash.h:170
NvU8 SubSectorSize
SubSectorSize: SubSector Size of the flash (power of 2)
Definition: qspi_flash.h:173
Holds QSPI Transfer data.
Definition: qspi.h:114
NvU8 SectorSize
SectorSize: Sector Size of the flash (power of 2)
Definition: qspi_flash.h:167
struct QspiAsyncIOStatus QspiAsyncIOStatus_t
Holds the QSPI Asynchronous transfer descriptor.
QspiFlashInfo_t * pFlashInfo
QSPI flash information.
Definition: qspi_flash.h:201
Holds the QSPI Flash device context.
Definition: qspi_flash.h:185
struct QspiFlashInfo QspiFlashInfo_t
QSPI flash info.
struct QspiFlashDevice QspiFlashDevice
Holds the QSPI Flash device context.
struct QspiFlashInfo QbFlashInfoList[]
QspiTransfer Transfers[3]
Transfer data structure for , , .
Definition: qspi_flash.h:195
Holds QSPI hardware controller context data.
Definition: qspi.h:129
QspiControllerData * pControllerData
Describes the QSPI hardware controller-specific data.
Definition: qspi_flash.h:204
NvError
The NvError enumeration contains ALL return / error codes.
Definition: nverror.h:36
QSPI flash info.
Definition: qspi_flash.h:152
QspiXferStatus_t Status
Ongoing or complete.
Definition: qspi_flash.h:142
NvU32 BytesRemaining
Remaining bytes after async transfer is complete.
Definition: qspi_flash.h:141
NvU32 Offset
Offset in QSPI flash that specifies where the async transfer completed.
Definition: qspi_flash.h:145
NvU8 SubSectorCnt
SubSectorCnt: SubSector count of the flash.
Definition: qspi_flash.h:176
Holds the QSPI Asynchronous transfer descriptor.
Definition: qspi_flash.h:139
QspiFlashDevice * ps_QspiFlash[QSPI_FLASH_MAX_INSTANCES]
NVIDIA Quickboot Interface: Error Handling (Parker)
#define QSPI_FLASH_MAX_INSTANCES
Defines the number of flash chips.
Definition: qspi_flash.h:38
void * Buffer
Buffer address from which transfer can resume.
Definition: qspi_flash.h:146
NVIDIA Quickboot Interface: QSPI Access
QspiAsyncIOStatus_t AsyncStatus
QSPI Asynchronous transfer data.
Definition: qspi_flash.h:198
NvU8 Density
Density: Density of the flash.
Definition: qspi_flash.h:164
NvS8 FlashName[32]
FlashName: Name of the Flash.
Definition: qspi_flash.h:155
NVIDIA Quickboot Interface: Device Drivers
NvU32 Instance
ID of Flash chip connected to QSPI controller.
Definition: qspi_flash.h:188
NvError QbQspiInit(void)
Performs QSPI flash driver initialization.
NvU8 ReadCommand
Command for reading from flash, which depends on the DDR/SDR mode.
Definition: qspi_flash.h:191