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5.1.3.0 Release

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sdmmc.h
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1 /*
2  * Copyright (c) 2010-2018, NVIDIA CORPORATION. All Rights Reserved.
3  *
4  * NVIDIA CORPORATION and its licensors retain all intellectual property
5  * and proprietary rights in and to this software, related documentation
6  * and any modifications thereto. Any use, reproduction, disclosure or
7  * distribution of this software and related documentation without an express
8  * license agreement from NVIDIA CORPORATION is strictly prohibited.
9  */
10 
27 #ifndef INCLUDED_SDMMC_H
28 #define INCLUDED_SDMMC_H
29 #include <device.h>
30 #include <clock_reg.h>
31 #include <nvboot_sdmmc_param.h>
32 
33 #define MAX_SDMMC_INSTANCE 4
34 
36 #define SDMMC_COMMAND_TIMEOUT_IN_US 100000
37 #define SDMMC_OP_COND_TIMEOUT_IN_US 1000000
39 #define SDMMC_READ_TIMEOUT_IN_US 200000
41 #define SDMMC_TIME_OUT_IN_US 100000
43 
45 #define NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES 16
46 #define NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES 512
48 #define NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES 512
50 
51 #define DEBUG_SDMMC 0
52 
55 typedef enum
56 {
69 
75 typedef enum
76 {
99  SdmmcCommand_Force32 = 0x7FFFFFFF
100 } SdmmcCommand;
101 
105 typedef enum
106 {
115  SdmmcState_Force32 = 0x7FFFFFFF
116 } SdmmcState;
117 
121 typedef enum
122 {
130 
134 typedef enum
135 {
141 
145 typedef enum
146 {
158 typedef enum
159 {
165 
170 typedef struct
171 {
173  NvU32 Instance;
181 
189 
191  NvBool Mantissa;
192 
194  NvBootSdmmcDataWidth DataWidth;
195 
196  /* Clock info */
197  QbClocksInfo SdmmcClock;
198 
199  /* Tap and Trim values */
200  NvU32 TapVal;
201  NvU32 TrimVal;
202 
203  /* AutoCal PD and PU offset */
206 
207  NvBool DisableHS400;
208 
211 
212  /* Tap value for incoming DQS path trimmer - used in HS400 modes */
213  NvU32 DqsTrimVal;
214 }QbSdmmcInfo;
215 
223 {
225  NvBool IsEsd;
233  NvU32 CardRca;
261  NvU8 taac;
263  NvU8 nsac;
265  NvU8 TranSpeed;
289  NvU32 NumOfBlocks;
299  NvU8 PowerClass52MHzDdr360V;//PWR_CL_DDR_52_360
301  NvU8 PowerClass52MHzDdr195V;//PWR_CL_DDR_52_195
303  NvU8 PowerClass200MHzDdr180V;//PWR_CL_DDR_200_180
305  NvU8 IsDdrMode;
307  NvBool IsPLLP;
308 
309  NvU32 RegPhyBase;
310  NvU32 RegLen;
311  NvU32 RegVirtBase;
315 
316  NvBool DisableHS400;
317  // Flag to indicate if the card is in ready state.
318  NvBool IsCardReady;
320 };
321 
322 /*
323  * Performs SDMMC driver initialization.
324  * Called by QB initialization code.
325  */
326 NvS32 QbSdmmcInit(void);
327 
328 NvError
329 QbSdmmcRead(QbDriver DriverType, NvU32 Instance, void *Buffer, NvU64 Size, NvU64 Offset);
330 
331 /*
332  * Debug function to dump sdmmc controller registers to console
333  */
334 void QbSdmmcDumpTegraRegs(NvU32 RegBase);
335 
336 /*
337  * Debug function to dump interrupt status registers
338  */
339 void QbSddmmcPrintInterruptStatus(NvU32 InterruptStatus);
341 #endif /* #ifndef INCLUDED_SDMMC_H */
SdmmcAccessRegion CurrentAccessRegion
Holds the current access region.
Definition: sdmmc.h:255
SdmmcResponseType
Defines command responses for eMMC/ESD.
Definition: sdmmc.h:55
NvU8 BootConfig
Holds the boot config from ExtCSD.
Definition: sdmmc.h:283
NvU8 PowerClass200MHzDdr180V
Power class for 200 Mhz DDR @ 3.6V.
Definition: sdmmc.h:303
QbDriver
Defines Quickboot device driver types.
Definition: device_id.h:34
NvU32 XferStartTime
Holds the Movi Nand Read/Write start time.
Definition: sdmmc.h:241
NvU8 SdmmcBootModeBuffer[NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES]
Holds data read in boot mode.
Definition: sdmmc.h:293
NvU8 PageSizeLog2ForCapacity
Holds the page size to use for card capacity calculation.
Definition: sdmmc.h:273
NvU32 CardRca
Holds the card's Relative Card Address.
Definition: sdmmc.h:233
NvBool IsCardReady
Definition: sdmmc.h:318
NvU32 TrimVal
Definition: sdmmc.h:201
SdmmcState
Defines eMMC/ESD card states.
Definition: sdmmc.h:105
void QbSddmmcPrintInterruptStatus(NvU32 InterruptStatus)
NvU8 PowerClass52MHzDdr360V
Power class for 52 Mhz DDR @ 3.6V.
Definition: sdmmc.h:299
SdmmcInitLevel SdmmcInitType
Definition: sdmmc.h:314
NvBool DisableHS400
Definition: sdmmc.h:316
NvU8 SdmmcInternalBuffer[NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES]
Defines a buffer for selecting high speed, reading extended CSD and SCR.
Definition: sdmmc.h:259
NvS32 QbSdmmcInit(void)
NvU32 TapVal
Definition: sdmmc.h:200
NvU8 taac
Defines read access time1.
Definition: sdmmc.h:261
NvU8 TranSpeedInMHz
Defines the transfer speed in MHz.
Definition: sdmmc.h:267
NvU8 ClockDivisor
Defines the clock divisor for the SDMMC Controller Clock Source.
Definition: sdmmc.h:180
QbDeviceStatus
Defines the current status of a transfer request.
Definition: device.h:48
NvBool IsHighCapacityCard
Defines whether the card is a high capacity card.
Definition: sdmmc.h:247
NvU32 SdmmcResponse[NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES/sizeof(NvU32)]
Holds a response buffer.
Definition: sdmmc.h:237
NvU32 NumOfBlocks
Holds the number of blocks present in card.
Definition: sdmmc.h:289
SdmmcInitLevel
Defines various initialization optimization options.
Definition: sdmmc.h:158
NvU8 PagesPerBlockLog2
Holds the number of pages per block.
Definition: sdmmc.h:231
NvU32 DqsTrimVal
Definition: sdmmc.h:213
NvBool IsHighVoltageRange
Defines whether high voltage range is used for card identification.
Definition: sdmmc.h:285
NvBootSdmmcDataWidth DataWidth
Defines the data bus width.
Definition: sdmmc.h:194
NvBool EnhancedStrobeMode
Defines whether to access the card in HS400 ESM.
Definition: sdmmc.h:245
NvU8 PowerClass26MHz195V
Holds the power class for 26MHz at 1.95V.
Definition: sdmmc.h:279
#define NVBOOT_SDMMC_ECSD_BUFFER_SIZE_IN_BYTES
Defines the buffer size for reading extended CSD.
Definition: sdmmc.h:47
NvError
The NvError enumeration contains ALL return / error codes.
Definition: nverror.h:36
NvU8 PageSizeLog2
Holds the page size.
Definition: sdmmc.h:229
NvU8 TranSpeed
Defines the clock frequency when not in high speed mode.
Definition: sdmmc.h:265
NvBool CardSupportsHighSpeedMode
Defines whether the card supports high speed mode.
Definition: sdmmc.h:271
SdmmcAccessRegion
Defines eMMC card partitions.
Definition: sdmmc.h:121
NvBool IsPLLP
Indicates whether Parent clock source is PLLP or PLLC4.
Definition: sdmmc.h:307
NvU32 AutoCalPuOffset
Definition: sdmmc.h:205
NvU32 VendorClockCtrl
Definition: sdmmc.h:313
NvU8 PowerClass52MHzDdr195V
Power class for 52 Mhz DDR @ 1.95V.
Definition: sdmmc.h:301
NvU8 nsac
Defines read access time2.
Definition: sdmmc.h:263
NvU8 IsDdrMode
Indicates whether Ddr mode is used for data transfer.
Definition: sdmmc.h:305
QbClocksInfo SdmmcClock
Definition: sdmmc.h:197
#define NVBOOT_SDMMC_BOOT_MODE_BUFFER_SIZE_IN_BYTES
Defines the buffer size for reading data in boot mode.
Definition: sdmmc.h:49
NvU16 CardClockDivisor
Defines a value for subdividing the clock that goes to the card from the controller.
Definition: sdmmc.h:188
NvBootSdmmcCardClock CurrentClockRate
Holds the current clock rate.
Definition: sdmmc.h:257
NvU8 MaxPowerClassSupported
Holds the Max Power class supported by target board.
Definition: sdmmc.h:287
NvU8 SpecVersion
Holds the spec version.
Definition: sdmmc.h:249
NvBool BootModeReadInProgress
Defines whether you are reading in boot mode.
Definition: sdmmc.h:295
NvError QbSdmmcRead(QbDriver DriverType, NvU32 Instance, void *Buffer, NvU64 Size, NvU64 Offset)
QbDeviceStatus DeviceStatus
Holds the device status.
Definition: sdmmc.h:239
NvU8 PowerClass52MHz360V
Holds the power class for 52MHz at 3.6V.
Definition: sdmmc.h:277
NvU32 XferTimeOutInUs
Holds read/write time out at current card clock frequency.
Definition: sdmmc.h:291
QbSdmmcInfo * pdata
Definition: sdmmc.h:312
NvU8 ExtCsdSpecVersion
Holds the ExtCsdSpecVersion.
Definition: sdmmc.h:251
NvU8 CardSupportSpeed
Flag to indicate the card speed and operating voltage level.
Definition: sdmmc.h:297
NvBool Support64BitDmaAddr
Definition: sdmmc.h:319
NvU32 Instance
Defines the SDMMC controller instance ID.
Definition: sdmmc.h:173
NvBool DisableHS400
Definition: sdmmc.h:207
Defines platform data for the SDMMC registration.
Definition: sdmmc.h:170
NvBootSdmmcCardClock
Defines various clock rates to use for accessing the eMMC/ESD card.
Definition: sdmmc.h:145
SdmmcCommand
Defines eMMC/ESD commands as per eMMC/ESD specifications.
Definition: sdmmc.h:75
NVIDIA Quickboot Interface: Device Drivers
NvU8 BlockSizeLog2
Holds the block size.
Definition: sdmmc.h:227
NvBool HighSpeedMode
Defines whether to access the card in high speed mode.
Definition: sdmmc.h:243
NvU8 PowerClass26MHz360V
Holds the power class for 26MHz at 3.6V.
Definition: sdmmc.h:275
Holds the context structure for the SDMMC driver.
Definition: sdmmc.h:222
#define NVBOOT_SDMMC_RESPONSE_BUFFER_SIZE_IN_BYTES
Defines the SDMMC response buffer size.
Definition: sdmmc.h:45
NvBootSdmmcCardType
Defines the supported card types.
Definition: sdmmc.h:134
SdmmcInitLevel SdmmcInitType
Definition: sdmmc.h:209
NvBool Support64BitDmaAddr
Definition: sdmmc.h:210
NvBool HostSupportsHighSpeedMode
Defines whether the host supports high speed mode.
Definition: sdmmc.h:269
void QbSdmmcDumpTegraRegs(NvU32 RegBase)
NvU8 PowerClass52MHz195V
Holds the power class for 52MHz at 1.95V.
Definition: sdmmc.h:281
NvBool Mantissa
Indicates whether to add 0.5 to ClockDivisor.
Definition: sdmmc.h:191
NvBool IsEsd
Defines whether the driver is for an ESD card (vs eMMC).
Definition: sdmmc.h:225
NvU32 AutoCalPdOffset
Definition: sdmmc.h:204
NvU32 EmmcBootPartitionSize
Holds Emmc Boot Partition size.
Definition: sdmmc.h:253