> For clean Markdown of any page, append .md to the page URL. > For a complete documentation index, see https://docs.nvidia.com/dsx/llms.txt. > For AI client integration (Claude Code, Cursor, etc.), connect to the MCP server at https://docs.nvidia.com/dsx/_mcp/server. # BESS Qualification Overview > Application Note defining the partner-run qualification process for Battery Energy Storage Systems intended to support AI load buffering, demand response, and low voltage ride-through. ## Step 1: Product Requirements Document (PRD) Review Partner must respond to each PRD requirement line with: * **Compliant / Non-compliant / Exception** (C, D, or E) * For non-compliance: current behavior, roadmap, workaround, and risk * For exceptions: explain the technical substitute and results * Reference to specific evidence: test ID, plot, model, or certificate Reference document: **"BESS Requirements Document"** ### Table 1. BESS Qualification PRD Response Example | Requirement ID | Item | Description | Partner Response | | -------------- | ------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ----------------------------------------- | | CTRL-REQ-01 | Grid-Adaptive | PCS shall sustain stable island mode operation, including voltage and frequency control independent of grid synchronization signals such as a phase-locked loop (PLL). | Compliant. Evidence: Test 9, EMT case E-4 | | PERF-REQ-02 | Ramp limit | Demonstrate active ramp-rate smoothing to buffer the source from sudden AI load swings. The system must maintain constant stability between the source and the load, ensuring no oscillations or control 'hunting' occur during rapid power transitions or under normal load conditions. | Compliant. Evidence: Test 4, 5 and 11 | #### Note Since the qualification boundary is at BESS AC terminals, "POI ramp" requirements are verified using an approved POI proxy: a commanded P profile equivalent to the required POI shaping, and/or EMT verification using partner-provided models. ## Step 2: Materials, Safety, and Compliance Disclosure Partner must complete disclosure tables for: ### 2.1 Battery and PCS Materials and Safety * Cell chemistry, enclosure type, fire detection/suppression approach * Cooling method (air/liquid), coolant type (if applicable) * Dielectrics/insulation class for major components * Hazardous materials declaration (electrolyte class, refrigerants) ### 2.2 Standards and Regulatory Compliance Evidence Provide certificates or reports for: * UL 9540 / UL 9540A (or equivalent) status * NFPA 855 alignment statement * IEEE 2800 functional alignment statement (even if not certified) * CE/UKCA (where applicable) * RoHS/REACH * EMC compliance evidence relevant to PCS ## Step 3: Core Requirements Availability A subset of requirements is designated Core Requirements representing minimum essential capabilities to pass qualification. Partners must complete the "Core Requirements Checklist" provided in Appendix B. ### Table 2. Core Requirements (Minimum) | No. | Core Requirement | Requirement ID | Minimum Requirement | | --- | -------------------------------------- | -------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | 1 | Autonomous Island Operation Capability | CTRL-CORE-01 | PCS shall stably transition to and sustain island mode operation. Loss of external voltage reference shall not cause voltage and frequency regulation to exceed specified performance limits. Voltage source behavior under current limit. Defined virtual impedance or equivalent mechanism. | | 2 | AI buffering dynamic response | PERF-CORE-01 | Demonstrate active ramp-rate smoothing to buffer the source from sudden AI load swings. The system must maintain constant stability between the source and the load, ensuring no oscillations or control 'hunting' occur during rapid power transitions or under normal load conditions. | | 3 | Current limit behavior | PERF-CORE-02 | Current limiting shall be predictable: no unstable oscillation, no uncontrolled voltage collapse in modeled grid conditions. | | 4 | LVRT/HVRT | GRID-CORE-01 | Support IEEE 2800 ride-through behavior as baseline; utility curves may supersede. | | 5 | Reactive power support | GRID-CORE-02 | Provide voltage support via Q within PCS current limits; document Q priority rules. | | 6 | Seamless grid/island transition | MODE-CORE-01 | Demonstrate controlled transitions without loss of synchronism or unstable control mode hunting. Transition performance shall be quantified using voltage deviation per ANSI C84.1 and dynamic voltage/frequency ride-through per IEEE 2800. | | 7 | Black start | MODE-CORE-02 | Demonstrate black-start energization of a dead bus and stable V/f regulation. | | 8 | Telemetry and controls | TELE-CORE-01 | Real-time reporting of V, I, P, Q, f, SOC, alarms, and limit states. Must support 3 concurrent Modbus TCP connections with all points being polled at 1 second frequency. SOC values must be included in all telemetry reporting. | | 9 | Control transparency artifacts | MODEL-CORE-01 | Provide EMT model + validation against impedance/admittance scan (dq impedance vs frequency) + Nyquist/passivity artifacts. Comply with NERC Reliability Guidelines. | | 10 | DR dispatch capability | OPS-CORE-01 | Follow dispatch setpoints with defined response time, ramp limits, and SOC reserve logic. | ## Step 4: Qualification Tests This section defines test procedures and pass/fail criteria. All tests are performed at the BESS AC terminals unless explicitly stated as model-only. ### Table 3. Instrumentation Requirements (applies to all tests) **Minimum measurement accuracy (applies to all tests):** | Parameter | Minimum Accuracy | Sampling Rate | | ----------------------------------------------- | ---------------------------------- | ------------------------------------- | | Voltage | ±0.2% of reading | ≥ 5 kHz (EMT) / ≥ 10 Hz (operational) | | Current | ±0.2% | ≥ 5 kHz (EMT) / ≥ 10 Hz (operational) | | Power (P/Q) | ±0.5% | ≥ 10 Hz | | Frequency | ±0.01 Hz | ≥ 10 Hz | | Time Sync | ±1 ms between channels | N/A | | P/Q Dynamic (ramp, oscillations and transients) | ±0.1% of rated P at test frequency | ≥ 120 Hz | | Bandwidth | 0.1–59.9 Hz | — | All events must include pre-trigger (≥ 5 s) and post-trigger (≥ 20 s) unless otherwise specified.