> For clean Markdown of any page, append .md to the page URL.
> For a complete documentation index, see https://docs.nvidia.com/holoscan/sensor-bridge/llms.txt.
> For AI client integration (Claude Code, Cursor, etc.), connect to the MCP server at https://docs.nvidia.com/holoscan/sensor-bridge/_mcp/server.

## Clocking

There are 4 main clocks in the system, host interface (HIF), APB interface, sensor
interface (SIF), and PTP interface clocks.

The Host Interface signals connect to transmit or receive data from the Ethernet MAC.
Therefore, the Host Interface bandwidth (clock frequency x data width) should support
the Ethernet bandwidth of the design.

For example, when integrating the Holoscan Sensor Bridge IP in 10G application, a common
clock frequency and data width used is 156.25MHz and 64 bits respectively. If the system
Ethernet MAC outputs a 156.25MHz, a possible design is to use the same Ethernet MAC
output clock as the Host Interface clock. If the system cannot use the Ethernet MAC
clock directly, then a dual clock FIFO can be used to match the bandwidth of the
Ethernet MAC. Ultimately, the clock architecture is determined by the intended
application and FPGA vendor used for the Holoscan Sensor Bridge IP.

The Sensor Interface clocks (i\_sif\_rx\_clk and i\_sif\_tx\_clk) drives the frontend sensor
AXI-Stream interface. Each sensor AXI-Stream interface has a dedicated clock input that
can operate at an independent frequency.

The sensor AXI-Stream signals are crossed into the Host Interface clock domain using a
dual clock FIFO within the Holoscan Sensor Bridge IP.

## Resets

The Holoscan Sensor Bridge IP outputs resets synchronous to respective clocks from 1
main asynchronous reset input.

The input reset port (i\_sys\_rst) is an active-high, asynchronous reset. This port should
be connected to the board reset pin (RESET, active-high, in the diagram) gated with the
PLL locked signal. This will assert the reset to the Holoscan Sensor Bridge IP until the
PLL is locked.

Example connection of the input and output resets are shown below.

![External\_Reset](https://fdr-prod-docs-files-public.s3.us-east-1.amazonaws.com/nvidia-holoscan.docs.buildwithfern.com/c3c0971d5617e4d704de708dfd296cfe9a5cf82b09c4805ee7cdc2d85bde5ef8/_dot_dot_/images/clocking_and_reset/External_Reset.png?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Content-Sha256=UNSIGNED-PAYLOAD&X-Amz-Credential=AKIA6KXJSKKNFOCF7G4B%2F20260727%2Fus-east-1%2Fs3%2Faws4_request&X-Amz-Date=20260727T002411Z&X-Amz-Expires=604800&X-Amz-Signature=ba687716e003998a7590763cbab7b20faa957297f64bd736c103f833ea334c92&X-Amz-SignedHeaders=host&x-amz-checksum-mode=ENABLED&x-id=GetObject)

Figure 1 Reference Design Reset Connections

Table below describes the various output resets and its clocking relations when
asserting and deasserting.

Table 1 Reset Assertion and Deassertion

| Reset                               | Assertion                  | Deassertion                            | Description                                                                                                                                                 |
| ----------------------------------- | -------------------------- | -------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------- |
| o\_apb\_rst                         | Asynchronous               | Synchronous to i\_apb\_clk             | Can be used to reset APB logic outside of IP                                                                                                                |
| o\_hif\_rst                         | Asynchronous               | Synchronous to i\_hif\_clk             | Can be used to reset Host logic outside of IP<br />Reset is deasserted after o\_apb\_rst is deasserted.                                                     |
| o\_sif\_rx\_rst\[N-1:0]<sup>1</sup> | Asynchronous               | Synchronous to i\_sif\_rx\_clk\[N-1:0] | Can be used to reset Sensor Interface logic outside of IP<br />Reset is deasserted after o\_apb\_rst is deasserted.                                         |
| o\_sif\_tx\_rst\[M-1:0]<sup>1</sup> | Asynchronous               | Synchronous to i\_sif\_tx\_clk\[M-1:0] | Can be used to reset Sensor Interface logic outside of IP<br />Reset is deasserted after o\_apb\_rst is deasserted.                                         |
| o\_ptp\_rst                         | Asynchronous               | Synchronous to i\_ptp\_clk             | Can be used to reset PTP logic outside of IP<br />Reset is deasserted after o\_apb\_rst is deasserted.                                                      |
| o\_sw\_sen\_rst                     | Synchronous to i\_hif\_clk | Synchronous to i\_hif\_clk             | Register controlled sensor reset.<br />Can be connected to FPGA I/O to reset sensors on board.                                                              |
| o\_sw\_sys\_rst                     | Synchronous to i\_hif\_clk | Synchronous to i\_hif\_clk             | Register controlled system reset. Can be used to reset system level logic.<br />This will also trigger reset for o\_hif\_rst, o\_apb\_rst, and o\_sif\_rst. |

1. N=`SENSOR_RX_IF_INST`, M=`SENSOR_TX_IF_INST`