This topic describes how to port NVIDIA® Jetson™ Linux Driver Package (L4T) From NVIDIA® Jetson AGX Xavier™ Developer Kit to another hardware platform.

The examples described include code for the Jetson AGX Xavier Developer Kit (P2972).

For information on customizing the configuration files, see the topics Jetson AGX Xavier MB1 Platform Configuration and “Configuring Pinmux, GPIO and PAD.”

Jetson AGX Xavier Developer Kit consists of a P2888 System on Module (SOM) connected to a P2822 carrier board. Part number P2972 designates the complete Jetson AGX Xavier Developer Kit. The SOM and carrier board each have an EEPROM where the board ID is saved. The SOM can be used without any software configuration modifications.

The SOM sold for incorporation into customer products has a Thermal Transfer Plate (TTP) ready to accept a customer-provided thermal solution. The module shipped as part of the Developer Kit has no TTP; instead it has a thermal solution designed specifically for the Developer Kit. This thermal solution must not be removed from the module.

To support a Jetson AGX Xavier module with your carrier board, you must assign the module/carrier board combination a lower case alphanumeric name. The name may include hyphens (-) and underscores (_), but not spaces. Some examples of valid names are:

The name you select appears in:

Additionally, this name is exposed to the user through various Linux kernel proc files.

In this topic, <board> represents your board name.

You must also select a similarly-constructed vendor name. The same character set rules apply, such as the following example:

In this topic, <vendor> represents your vendor name.

Placeholders are used throughout this topic, substitute an appropriate value for each placeholder when executing commands.

The table below describes camera connector pin differences between the Jetson AGX Xavier module and the earlier NVIDIA® Jetson™ TX1 and Jetson TX2 modules.

In summary, the Jetson AGX Xavier module:

L4T can use any standard or customized Linux root filesystem (rootfs) that is appropriate for their targeted embedded applications.

However, certain settings must be configured in the rootfs’s boot-up framework to set default configuration after boot, or some of the core functionalities will not run as expected.

For example:

These rootfs configurations and customizations are provided in this driver package in the directory and its subdirectories:

You must incorporate the relevant customization for your target rootfs from this location.

Multiple .cfg files define boot time configuration of the hardware. They are applied by Bootloader. The MB1 boot configuration tables are available at:

If your board schematic differs from that for Jetson AGX Xavier Developer Kit board, you must change the pinmux configuration applied by the software.

The Jetson-AGX-Xavier-Generic-Customer-Pinmux-Template.xlsm spreadsheet is provided to:

You must customize the spreadsheet for the configuration of your board.

Once done, you must convert the .dtsi file generated by Excel to a .cfg. For instructions, see the README file at:

You must perform the same conversion for gpio.dtsi and padvoltage.dtsi.

If you designed your own carrier board, to translate from SOM connector pins to actual GPIO numbers you must understand GPIO mapping formula below. The translated GPIO numbers can be controlled by the driver.

For example, to check the GPIO number of SLVS_HSYNC, perform the following steps.

The PMIC configuration file configures the initial PMIC in the P2888 SOM. Some GPIO expander-based GPIO regulator settings in the P2822 carrier board configurations are also defined. Review this configuration file to replace any references to the P2822 carrier board to your custom board. If required, include any regulator information to enable this file.

It is assumed that you are using a P2888 SOM connected to a P2822 carrier board which have not been modified; the eMMC, PMIC, and DDR are the same with the same routing of lines. The modifications you are making are for the SOM and the carrier board. Consequently, based on the peripherals present on your carrier board, you can modify the .dts files by disabling/enabling the controllers and changing the supplies.

To port the kernel configuration code (the device tree) to your platform, modify one of the distributed configuration files to describe the design of your platform.

The configuration files are available at:

The final DTB file used is:

By reading the above file, you see which other .dtsi files are referenced by include statements. Common .dtsi files that may be modified to reflect hardware design changes include:

Verify that no other .dts or .dtsi file, including these .dts files, overrides any changes you make.

As a best practice, create your own set of .dts files based on the Galen files already present. Rename your newly created files to the name of your board.

The PCIe host controller is based on Synopsis Designware PCIe intellectual property, and thus inherits all the common properties defined in the information file at:

Jetson AGX Xavier has six PCIe controllers with these specifications:

The Jetson AGX Xavier default PCIe configuration is:

These PCIe slots available on Jetson AGX Xavier:

For information about Jetson AGX Xavier specific PCIe controller configuration, see the device tree documentation file at:

This file covers topics that include configuring maximum link speed and link width, and advertisement of different ASPM states.

In the file at:

Jetson AGX Xavier can support up to four enhanced SuperSpeed USB ports. In some implementations not all of these ports can be used because of UPHY lane sharing among PCIE, SATA, UFS, and XUSB. The Jetson P2822 carrier board is designed and verified for three USB3.1 ports. If you designed your own carrier board, verify the UPHY lane mapping and compatibility between P2822 and your custom board by consulting the NVIDIA team.

An enhanced SuperSpeed USB port has nine pins:

The D+/D− signal pins connect to UTMI pads. The SSTX/SSRX signal pins connect to UPHY and are handled by a single UPHY lane. As UPHY lanes are shared between PCIE, SATA, UFS, and XUSB, UPHY lanes must be assigned according to the custom carrier board’s requirements.

UPHY is an acronym for universal physical layer, a physical I/O interface layer that can serve multiple types of interfaces, e.g. USB, PCIe, SATA, and UFS. A UPHY lane is a lane in UPHY which can support multiple types of interfaces.

The Jetson P2822 carrier board is designed and verified for three USB3.1 ports. The verified use cases and their UPHY lane assignments are shown in the following two tables.

Jetson AGX Xavier is designed to support the configurations listed in these tables. Released software also supports these configurations. For further information, consult NVIDIA Jetson AGX Xavier Technical Reference Manual (TRM) and consult with NVIDIA before designing your custom board.

This section gives step-by-step guidance for checking schematics and configuring USB ports in the device tree. All the examples are based on the design of Jetson AGX Xavier P2822 carrier board.

This section takes J513, a USB 3.1 type-C connector for example of a host-only port.

Through the schematic, we can conclude that for J513:

The device tree’s xusb_padctl node follows the conventions of the pinctrl-bindings.txt kernel document. It contains two sets of groups named pads and ports, which describe USB2 and USB3 signals along with parameters and port numbers. The name of each parameter description subnode in pads and ports must be in the form <type>-<port_number>, where <type> is "usb2" or "usb3" and <port_number> is the associated port number.

For the detailed information about xusb_padctl, refer to the documentation at:

Take J513 (USB3.1 type-C connector) for example. Create a pad/port node and property list for J513 based on the device tree structure described above:

The Jetson AGX Xavier xHCI controller complies to xHCI specifications, which support both USB 2.0 HighSpeed/FullSpeed/LowSpeed and USB 3.1 SuperSpeed protocols.

For detailed information about xHCI, refer to the documentation at:

Take J513 USB3.1 type-C connector for example. Create an xHCI node and property list for J513 based on the device tree structure described above:

USB On-The-Go, often abbreviated USB OTG or just OTG, is a specification that allows USB to act as a host or a device in the same port. A USB OTG port can switch back and forth between the roles of host and device.

This section takes J512, USB3.1 type-C connector, as an example of an OTG port.

An OTG port adds a fifth pin to the standard USB connector, called the ID pin. An OTG cable has an A-plug on one end and a B-plug on the other end. The A-plug’s ID pin is grounded, while the B-plug’s ID pin is floating. A device with an A-plug inserted becomes and OTG A-device (host), and a device with a B-plug inserted becomes a B-device (device).

Check the USB connectors on the P2822 carrier board and find the wired socket location to P2888.

Through the schematic, we can that for J513:

External connectors, which may have different types of cables attached (USB, TA, HDMI, Analog A/V, and others), often have device drivers that detect state changes at the port, and separate device drivers that do something according to the state changes.

The External Connector Class (extcon), introduced in 2012, supports the use of a notifier for passing information such as state changes between device drivers.

Generally, port switching between the roles of an OTG port is controlled by the host driver (xHCI) and device driver (xUDC), and can be defined by the state of the ID pin and the VBUS_DETECT pin.

Taking GPIO_M3 as the VBUS_DETECT pin and GPIO_Q0 as the ID pin, for example:

Port switching between the roles of an OTG port is defined by the state of the ID pin and the VBUS_DETECT pin and the settings of the external connector class.

For the detailed information about extcon, refer to the documentation at:

 

 

In the Jetson AGX Xavier Developer Kit role switching of port J512 between host driver (xHCI) and device driver (xUDC) modes is controlled by default by U513, a Cypress Type-C controller, and the ucsi_ccg driver.

The subnode names must be in the form port-<number>, where <number> is a integer with value 0 or 1 which represents the type-C port (J512/J513).

The name of the subnode must be pd.

For the detailed information about ucsi_ccg, refer to the driver source code at:

Taking J512 USB3.1 type-C connector as an example, create a ucsi_ccg node and property list based on the device tree structure described above for J512:

xusb_padctl settings for an OTG port are the same as for a host-only port except that the mode should be "otg".

Taking J512, the USB3.1 type-C connector, as an example, create a pad/port node and property list:

The xHCI settings for an OTG port are the same as for a host-only port except for the addition of extcon settings:

Taking J512, the USB3.1 type-C connector, as an example, create an xHCI node and property list based on the device tree structure described in Under the XHCI Node for a host-only port, plus the extcon settings above:

The Jetson AGX Xavier xUDC controller supports both USB 2.0 HighSpeed/FullSpeed and USB 3.1 SuperSpeed protocols.

For the detailed information about xUDC, refer to the documentation at:

Taking J512, the USB3.1 type-C connector, as an example, create an xUDC node and property list for J512 based on the device tree structure described above:

When flashing the build image, use your specific board name. The flashing script uses the configuration in the <board>.conf file during the flashing process.

flash.sh script updates the following environment variables based on board EEPROM and other parameters passed. If you want to give specific values to these variables, define them in the board-specific file board.conf to override the default values.

 

Here is an example of environment variable settings:

This section provides a checklist for the platform hardware bring-up process.

This section provides a checklist for the software bring-up process.