Debugging on Jetson Platforms

NVIDIA Jetson Linux Driver Package Software Features

Release 32.3 | December 10, 2019

Debugging Improvements

CoreSight Trace Sinks ETF and ETR

CoreSight AMBA Trace ID (ATID) Mapping

Jetson Nano, Jetson TX2 series, and Jetson TX1

Jetson AGX Xavier Only

Jetson devices support debugging tools that allow Jetson application developers to place the processor into known states and trace its behavior while running. The Jetson architecture’s debugging support provides:

• Reduced power leakage

• Enhanced security

• Availability of standard interfaces

This topic describes the debuggable blocks and their debugging strategies. Use this information to help determine why something may not be working in the software you have developed using NVIDIA® Jetson™ Board Support Package (BSP).

This topic also describes the software implementation of the hardware and software features in the Jetson processor family of Technical Reference Manuals (TRMs). Use the appropriate TRM as your primary source for information and debugging:

• For Jetson Nano and Jetson TX1: Tegra X1 (SoC) Technical Reference Manual

• For Jetson AGX Xavier™: Xavier Series (SoC) Technical Reference Manual

• For Jetson TX2 series processors: Tegra X2 (Parker Series SoC) Technical Reference Manual

Debugging Improvements

The following table describes improvements in debugging features for Jetson devices.

Hardware Feature Benefit	Jetson TX1 & Nano	Jetson TX2	Jetson AGX Xavier
Hardware interface to debugger.
JTAG (4-pin connector)	X	X	X
SWD (2-pin connector)	—	—	X
Debug interface connected to CPU via Debug Communication Channel with Memory Access Mode in v8. Debugger downloads & uploads code faster.	X	X	X
Debug connection to AXI-AP via JTAG or SWD). System access when CPUs are unavailable (powered down, dead, in reset, etc.).	X	X	X
AXI-AP 34-bit address can access MMIO & DRAM with requiring SMMU.	X	X	X
Connection to SNIC allows access to entire system.		X	X
Debugger accesses to memory are coherent.			X
CoreSight support via JTAG or SWD.
Connection to APE.	X	X	X
Connection to BPMP, SPE, & SCE.	—	X	X
Connection to RCE, PVA0, & PVA1.	—	—	X
Trace Storage circular buffer. Larger buffer yieldsd a longer duration trace. Buffer is preserved through WDT resets.	16 KiB	32 KiB	32 KiB

CoreSight Trace Sinks ETF and ETR

The following table describes CoreSight trace sink characteristics for Jetson. These characteristics include the corresponding Embedded Trace FIFO (ETF), ETR, and USB limits.

Characteristic	ETF (32 KiB)	DDR via ETR DMA	TPIU (AGX Xavier only)	USB
Throughput	41.58 Gbps @ 408 MHz, 128‑bit *	41.58 Gbps	800 Mbps	Real time processor tracing requires reduction of CPU frequency.
Intrusive	No	Yes	No	Yes
Available on commercial devices	Yes	Yes	Yes	Yes
Use Cases	Collect trace for watchdog reset; code optimization for the CCPLEX.	Collect trace for watchdog reset; code optimization for the CCPLEX. †	Collects trace for watchdog reset; code optimization for the CCPLEX. Tracing is limited to bandwidth speed.	Single-CPU trace at low frequency, or APE-only trace to avoid DRAM bandwidth saturation. Tracing is limited to USB speeds.
* Contact NVIDIA for higher frequency requirements. † Note the high bandwidth requirement at DDR = 25%.

CoreSight AMBA Trace ID (ATID) Mapping

The following tables describe mapping for CoreSight AMBA Trace ID (ATID). When collecting trace from multiple sources, the trace sinks (ETF and ETR) use ATIDs to segregate trace data.

Jetson Nano, Jetson TX2 series, and Jetson TX1

BCCPLEX (also called Fast Cluster or Big Cluster) using A57 processors
ATID	Processor	Protocol
0x40	CPU0	ETMv4
0x41	CPU1	ETMv4
0x42	CPU2	ETMv4
0x43	CPU3	ETMv4
APE, Cortex A9
ATID	Processor	Protocol
0x20	CPU0	PFT1.0
STM
ATID	Processor	Protocol
0x10	NA	MIPI STP

Jetson AGX Xavier Only

CCPLEX using NVIDIA processors
ATID	Processor	Protocol
N/A	CPU0−CPU7	N/A
Cortex R5
ATID	Processor	Protocol
Configurable	BPMP	ETMv3
Configurable	SPE	ETMv3
Configurable	SCE	ETMv3
Configurable	RCE	ETMv3
Configurable	PVA 0 and PVA1	ETMv3
APE, Cortex A9
ATID	Processor	Protocol
0x20	CPU0	PFT1.0
STM
ATID	Processor	Protocol
0x10	NA	MIPI STP