.. _SD.Bootloader.BootROMResetPMICConfig: .. include:: /content/swdocs.rsts .. spelling:: AO BootROM BR BCT dts CFG coldboot CPU BL tegrabct tegrabct_v2 Mem MB1 MB2 OEM FW SW VF HSM SC7 SC8 Watchdog PMIC OTP L1 L2 addr Ao AoBlock aoblock aotag hsm preinstalled sc vfsensor T23x Watchdog MAX77620 PMC MPL DPD SFT RST WK 7BIt BootROM Reset PMIC Configuration !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! For some T23x platforms, BootROM might be required to bring PMIC rails to OTP values in the L1 and L2 reset boot paths. This process is completed by issuing I2C commands, which are encoded in AO scratch registers by MB1, and are based on the BootROM reset configuration in MB1 BCT. - The reset cases where the BootROM issues these commands includes the following: - Watchdog 5 expiry - Watchdog 4 expiry - SC7 exit - SC8 exit - SW-Reset - AO-Tag/sensor reset - VF Sensor reset - HSM reset - Each reset case can have three sets of AO blocks of commands. - Each AO block has multiple blocks, and each block can have multiple commands. In the configuration file, AO blocks are specified first, and the reset conditions are initialized with the AO block IDs. Specifying AO Blocks #################### Each AO block-related line in the configuration file is of the following format: .. code-block:: none /{ - = <&AoBlock-Label> reset { : aoblock@ { = ; ... block@ { = ; }; }; : aoblock@ { ... } }; }; +---------------------+------------------+-------------------------------------+ | | | Description | +---------------------+------------------+-------------------------------------+ | - | <&AoBlock-Label> | - specifies the reset | | | | type and must have one of the | | | | values: watchdog5, watchdog4, | | | | sc7, sc8, soft-reset, | | | | sensor-aotag, vfsensor, or hsm. | | | | - is the index | | | | of the AO command and can have | | | | values 0, 1 or 2. Each reset path | | | | can point to a maximum of three | | | | Ao Blocks | | | | - is the label | | | | given to one of the Ao Blocks | +---------------------+------------------+-------------------------------------+ | aoblock@ | command-retries- | Specifies the number of command | | | count | attempts allowed for Ao-block with | | | | | | +------------------+-------------------------------------+ | | delay-between- | Specifies the delay (in | | | command-us | microseconds), in between different | | | | commands. The delay is calculated | | | | as 1 << n microseconds where n is | | | | provided by this parameter. | | +------------------+-------------------------------------+ | | wait-before- | Specifies the wait timeout (in | | | start-bus-clear- | microseconds), before issuing the | | | us | bus clear command for given AO | | | | block. The wait time is calculated | | | | as 1 << n microseconds where n is | | | | provided by this parameter. | +---------------------+------------------+-------------------------------------+ | block@ | | can only be one | | | | value - i2c-controller. That is the | | | | only one supported. | | +------------------+-------------------------------------+ | | count | Specifies the number of commands in | | | | the block | | +------------------+-------------------------------------+ | | i2c-controller | I2C controller instance | | | id | | | +------------------+-------------------------------------+ | | slave-addr | 7-bit I2C slave address | | +------------------+-------------------------------------+ | | reg-data-size | Register size in bits. Valid values | | | | are 0 (1-byte), 8 (1-byte), and 16 | | | | (2-byte) | | +------------------+-------------------------------------+ | | reg-addr-size | Register address size in bits. | | | | Valid values are 0 (1-byte), 8 | | | | (1-byte), and 16 (2-byte) | | +------------------+-------------------------------------+ | | commands | List of
pairs where | | | | value to be written to the I2C | | | | slave register address | | | | for the command indexed by | | | | | +---------------------+------------------+-------------------------------------+ Here is a new DTS example of the BootROM reset configuration file: .. code-block:: none /dts-v1/; / { reset { // Each reset path can point to upto three aoblocks // This is a map of reset paths to aoblocks // - = // index-number should be 0, 1 or 2 // aoblock-id is the id of the one of the blocks mentioned above sensor-aotag-1 = <&aoblock0>; sc7-1 = <&aoblock2>; aoblock0: aoblock@0 { command-retries-count = <1>; delay-between-commands-us = <1>; wait-before-start-bus-clear-us = <1>; block@0 { i2c-controller; slave-add = <0x3c>; // 7BIt:0x3c reg-data-size = <8>; reg-add-size = <8>; commands { command@0 { reg-addr = <0x42>; value = <0xda>; }; command@1 { reg-addr = <0x41>; value = <0xf8>; }; }; }; }; // Shutdown: Set MAX77620 // Register ONOFFCNFG2, bit SFT_RST_WK = <0> // Register ONOFFCNFG1, bit SFT_RST = <1> aoblock1: aoblock@1 { // Shutdown: Set MAX77620 // Register ONOFFCNFG2, bit SFT_RST_WK = <0> // Register ONOFFCNFG1, bit SFT_RST = <1> command-retries-count = <1>; delay-between-commands-us = <1>; wait-before-start-bus-clear-us = <1>; block@0 { i2c-controller; slave-add = <0x3c>; // 7BIt:0x3c reg-data-size = <8>; reg-add-size = <8>; commands { command@0 { reg-addr = <0x42>; value = <0x5a>; } ; command@1 { reg-addr = <0x41>; value = <0xf8>; }; }; }; }; // SC7 exit // Clear PMC_IMPL_DPD_ENABLE_0[ON]=0 during SC7 exit aoblock2: aoblock@2 { command-retries-count = <1>; delay-between-commands-us = <256>; wait-before-start-bus-clear-us = <1>; block@0 { mmio; commands { command@0 { reg-addr = <0x0c360010>; value = <0x0>; }; }; }; Here is the previous CFG format: .. code-block:: none // CFG Version 1.0 // This contains the BootROM commands in MB1 for multiple reset paths. reset.major = 1; reset.minor = 0; // Automatic power cycling: Set MAX77620 // Register ONOFFCNFG2, bit SFT_RST_WK = 1 (default is "0" after cold boot), // Register ONOFFCNFG1, bit SFT_RST = 1 reset.aoblock[0].command-retries-count = 1; reset.aoblock[0].delay-between-commands-us = 1; reset.aoblock[0].wait-before-start-bus-clear-us = 1; reset.aoblock[0].block[0].type = 1; // I2C Type reset.aoblock[0].block[0].slave-add = 0x3c; // 7BIt:0x3c reset.aoblock[0].block[0].reg-data-size = 8; reset.aoblock[0].block[0].reg-add-size = 8; reset.aoblock[0].block[0].commands[0].0x42 = 0xda; reset.aoblock[0].block[0].commands[1].0x41 = 0xf8; // Shutdown: Set MAX77620 // Register ONOFFCNFG2, bit SFT_RST_WK = 0 // Register ONOFFCNFG1, bit SFT_RST = 1 reset.aoblock[1].command-retries-count = 1; reset.aoblock[1].delay-between-commands-us = 1; reset.aoblock[1].wait-before-start-bus-clear-us = 1; reset.aoblock[1].block[0].type = 1; // I2C Type reset.aoblock[1].block[0].slave-add = 0x3c; // 7BIt:0x3c reset.aoblock[1].block[0].reg-data-size = 8; reset.aoblock[1].block[0].reg-add-size = 8; reset.aoblock[1].block[0].commands[0].0x42 = 0x5a; reset.aoblock[1].block[0].commands[1].0x41 = 0xf8; // SC7 exit // Clear PMC_IMPL_DPD_ENABLE_0[ON]=0 during SC7 exit reset.aoblock[2].command-retries-count = 1; reset.aoblock[2].delay-between-commands-us = 256; reset.aoblock[2].wait-before-start-bus-clear-us = 1; reset.aoblock[2].block[0].type = 0; // MMIO Type reset.aoblock[2].block[0].commands[0].0x0c360010 = 0x0; // Shutdown in sensor/ao-tag // no commands for other case reset.sensor-aotag.aocommand[0] = 1; reset.sc7.aocommand[0] = 2;