.. _AT.JetsonLinuxDevelopmentTools.DebuggingOnJetsonPlatforms: .. include:: /content/swdocs.rsts .. spelling:: CoreSight Perfmon uncore Uncore debuggable JTAG BCT bct MB1 ODM NIDEN APE DCE PVA0 PCE SCE SPE Ramdump FSI DBGEN SPIDEN SPNIDEN DEVICEEN BR ECID UID Debugging on Jetson Platforms !!!!!!!!!!!!!!!!!!!!!!!!!!!!! Jetson devices support debugging tools that allow Jetson application developers to put the processor into known states and trace its behavior while running. Use these tools to debug software you have developed using NVIDIA Jetson Board Support Package (BSP). The Jetson architecture’s debugging support provides: * Reduced power leakage * Enhanced security * Availability of standard interfaces This topic describes the debuggable blocks, their debugging strategies, and the software implementation of the hardware and software features in the Technical Reference Manuals (TRMs) for Jetson processors. Use the appropriate TRM as your primary source for information and debugging. .. todo:: Orin tbd. - For Jetson Xavier NX series and Jetson AGX Xavier series processors: `Xavier Series (SoC) Technical Reference Manual `_ Debugging Improvements @@@@@@@@@@@@@@@@@@@@@@ The following table describes improvements in debugging features for Jetson devices. .. raw:: html :file: DebuggingOnJetsonPlatforms/DebuggingImprovements.htm CoreSight Trace Sinks ETF and ETR @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ The following table describes ARM\ |reg| CoreSight\ |tm| trace sink characteristics for Jetson processors. These characteristics include the corresponding Embedded Trace FIFO (ETF), ETR, and USB limits. .. raw:: html :file: DebuggingOnJetsonPlatforms/CoreSightTraceSinks.htm AMBA Trace ID (ATID) Mapping @@@@@@@@@@@@@@@@@@@@@@@@@@@@ The following tables describe mapping for ARM AMBA Trace ID (ATID). When collecting trace from multiple sources, the trace sinks (ETF and ETR) use ATIDs to segregate trace data. .. todo:: Orin tbd .. raw:: html :file: DebuggingOnJetsonPlatforms/AmbaXavier.htm Uncore: Performance Monitor Unit @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ **Applies only to** the Jetson AGX Xavier series and Jetson NX series. Several functional units on the T194 CCPLEX (for example, the SCF and the L2) are outside the cores. These units are collectively referred to as the uncore. Some of them report uncore performance events and event counters, which are not counted by the core performance counters of the core’s Performance Monitor Unit (PMU). The NVIDIA Uncore Perfmon Extension to the ARM Performance Monitor Extension (also known as “Uncore Perfmon”) allows ARM software to access its performance counters. The Uncore Perfmon Extension is designed to resemble the standard ARM Performance Monitor Extension as much as possible. You can download `ARM PMU documentation `_ from the Linux Kernel Archives. Device-Specific Features and Limitations ######################################## This section describes features and limitations of Uncore Perfmon on specific Jetson systems on chip (SoCs). .. todo:: Orin tbd - For T194 modules (Jetson Xavier NX series and Jetson AGX Xavier series): - Uncore Perfmon events are supported for all cores and clusters. - For more information about using the counters, see the kernel documentation in source code at:: /Documentation/devicetree/bindings/platform/tegra/nvidia,carmel-pmu.txt Enabling JTAG Support on Secure Targets @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ On secure targets, where the ODM production fuse has been blown, MB1 locks the JTAG connection interface. To enable the Joint Test Action Group (JTAG) interface on such a target, a special BCT is required where certain parameters are set. Enabling the JTAG Interface on a Secure Target ############################################## #. Set the desired debugging features through the BCT section of the flashing configuration file. #. Generate a new BCT image. Enabling Debugging Features Through the BCT Configuration File ############################################################## #. In the BCT partition of the flashing configuration file, if you need to update the debug features in ``SecureDebugControlEcid``, set the UID attribute to the UID of the target device . #. To specify the debugging features that you want, set the ``SecureDebugControlEcid`` or ``u32_secure_debug_control_ecid_checked`` fields. The following table provides a list of the ``SecureDebugControlNoneEcid`` attribute collection of bit fields: .. list-table:: :widths: auto :header-rows: 1 * - Bits - Feature Enabled by a ``1`` Bit * - 31:18 - Reserved * - 17 - FSI non-secure NIDEN * - 16 - Reserved * - 15 - APE secure debug * - 14 - DCE secure debug * - 13 - Reserved * - 12 - PVA0 secure debug * - 11 - RCE secure debug * - 10 - SCE secure debug * - 9 - SPE secure debug * - 8.5 - Reserved * - 4 - NIDEN (disabled when DEBUG_AUTHENTICATION(1) fuse set) * - 3.0 - Reserved The following table provides a list of the ``SecureDebugControlEcid`` attribute collection of bit fields: .. list-table:: :widths: auto :header-rows: 1 * - Bits - Feature Enabled by a ``1`` Bit * - 31:18 - Ramdump * - 30.26 - Reserved * - 25 - FSI secure NIDEN * - 24 - FSI secure NIDEN * - 23:20 - FSI Cluster core debug [3:0] * - 19 - FSI non-secure NIDEN * - 18 - FSI non-secure NIDEN * - 17 - FSI non-secure NIDEN * - 16 - FSI non-secure NIDEN * - 5 - DBGEN * - 4 - NIDEN * - 3 - SPIDEN * - 2 - SPNIDEN * - 1 - DEVICEEN * - 0 - JTAG_ENABLE On secure targets, MB1 compares the UID of the chip to the UID in the BCT, and if the UIDs match, enables the debug features for ``SecureDebugControlEcid``. MB1 enables debug features for ``SecureDebugControlNoneEcid`` without verifying the UID. The following example has additional instructions on how to get ECID and convert it into BCT format: #. Get ECID. .. code-block:: none Linux_for_Tegra$ ./bootloader/tegrarcm_v2 --new_session --chip 0x23 --uid BR_CID: 0x80012344705E35C98800000002018080 #. Convert the ECID to BCT format. .. code-block:: none Input: 0x80012344,705E35C9,88000000,02018080 (ECID0, ECID1, ECID2, ECID3) Output: 0x02018080 0x88000000 0x705e35c9 0x00000004 where: 0x02018080 - ECID3 0x88000000 - ECID2 0x705e35c9 - ECID1 0x00000004 - First four bits from LSB of ECID0 #. To enable debug in BR BCT, make the following change: .. code-block:: none / { brbct { ECID = <0x02018080 0x88000000 0x705E35C9 0x00000004>; SecureDebugControlEcid = <0x3FF003F>;