.. _HR.JetsonModuleAdaptationAndBringUp.JetsonAgxXavierSeries: .. include:: /content/swdocs.rsts .. spelling:: ccg debounce Designware extcon Fi isoc usic padctl reflash subnode typec ucsi Wi xHCI Xorg xUDC xusb usb gpio VBus wakeup phandle Jetson Module Adaptation and Bring-Up: Jetson AGX Xavier Series !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! This topic is for engineers who are developing production software for an NVIDIA |Jetson AGX Xavier(tm)| series module. It describes how to port NVIDIA Jetson Linux and Bootloader from a Jetson AGX Xavier Developer Kit to a custom hardware platform and bring up a working system on the new platform. .. todo:: This paragraph originally referred to U-Boot. What wording is appropriate now that no supported platforms use U-Boot? The examples described include code for the Jetson AGX Xavier Developer Kit (P2972). For information on customizing the configuration files, see the section :ref:`MB1 Platform Configuration `. Two other topics are closely related to this one: - :ref:`Jetson Module Adaptation and Bring-Up: Checklists ` contains lists of steps to perform to complete the parts of the adaptation task. .. todo:: Need to add back the bring-up framework when it is ready for K5.10. Board Configuration @@@@@@@@@@@@@@@@@@@ .. todo:: In the context of the Development Guide, some or all of this may be redundant. What do you think? Jetson AGX Xavier Developer Kit consists of a P2888 System on Module (SOM) connected to a P2822 carrier board. Part number P2972 designates the complete Jetson AGX Xavier Developer Kit. The SOM and carrier board each have an EEPROM where the board ID is saved. The SOM can be used without any software configuration modifications. The SOM sold for incorporation into customer products has a Thermal Transfer Plate (TTP) ready to accept a customer-provided thermal solution. The module shipped as part of the Developer Kit has no TTP; instead it has a thermal solution designed specifically for the Developer Kit. This thermal solution must not be removed from the module. Before using the SOM with a carrier board other than P2822, change the kernel device tree, MB1 configuration, ODM data, and flashing configuration to include configuration for the new carrier board instead of for P2822. EEPROM ID for your custom board is not required. Board Naming @@@@@@@@@@@@ To support a Jetson AGX Xavier series module with your carrier board, you must assign the module/carrier board combination a lower case alphanumeric name. The name may include hyphens ("-") and underscores ("_"), but not spaces. Some examples of valid names are:: p2972-0000-devkit devboard The name you select appears in: - Filenames and pathnames - User-visible device tree filenames Additionally, this name is exposed to the user through various Linux kernel ``proc`` files. In this topic, ```` represents your board name. You must also select a similarly-constructed vendor name. The same character set rules apply, such as the following example:: nvidia In this topic, ```` represents your vendor name. .. note:: Do not re-use and modify the existing NVIDIA Jetson AGX Xavier Developer Kit code without selecting and using your own board name. If you do not use your own board name it will not be obvious to Jetson AGX Xavier series users whether the modified source code supports the original Jetson AGX Xavier Developer Kit board or your board. Placeholders in the Porting Instructions @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Placeholders are used throughout this topic, substitute an appropriate value for each placeholder when executing commands. - ```` is a functional module name, which may be ``power-tree``, ``pinmux``, ``sdmmc-drv``, ``keys``, ``comm`` (for Wi-Fi and Bluetooth\ |reg|), ``camera``, etc. - ```` is a name you have selected to represent your platform. For example, ``P2972`` is the name of the Jetson AGX Xavier Developer Kit. NVIDIA ```` names use lower case letters. - ```` is a board version number, such as ``a00``. Files for NVIDIA reference boards include a version number. Files for customer platforms are not required to include a version number. - ```` is the name of your organization, or the name of the vendor for your board. - ```` is the device that holds root file system for the platform. The supported value is ``emmc``. Camera Connector Pin Differences @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ The table below describes camera connector pin differences between Jetson AGX Xavier series modules and the earlier |NVIDIA(r)| |Jetson(tm)| TX1 and Jetson TX2 series modules. In summary, a Jetson AGX Xavier series module: - Adds four additional CSI lanes and places CSI6 where CSI5 was, and moves CSI5 to where UART and DMIC were - Removes the 1.2\ |nbsp|\ V and 5\ |nbsp|\ V rails (or changes 5\ |nbsp|\ V to 3.3\ |nbsp|\ V) - Removes UART, SPI, DMIC, and I2S - Removes Flash, Auto-Focus, and Strobe Control - Removes Motion Int and Modem to AP Ready .. raw:: html :file: JetsonAgxXavierSeries/CameraConnectorPinDifferences.htm For information about differences between other Jetson module pairs, see the `Interface Comparison documents `__ in the `Jetson Download Center `__. Root File System Configuration @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ Jetson Linux can use any standard or customized Linux root file system (rootfs) that is appropriate for their targeted embedded applications. However, certain settings must be configured in the rootfs’s boot-up framework to set default configuration after boot, or some of the core functionalities will not run as expected. For example: 1. The ``nv.sh`` and ``nvfb.sh`` boot-up scripts do some platform-specific configuration in the kernel. 2. The Xorg and X libraries must be correctly configured for the target device. 3. The nvpmodel clock and frequency must be configured for the target device. Jetson Linux provides these rootfs configurations and customizations in the directory ``Linux_for_Tegra/nv_tegra/`` and its subdirectories. You must incorporate the relevant customization for your target rootfs from this location. .. note:: For the sample Ubuntu root file system provided by NVIDIA, this customization is applied using the script ``Linux_for_Tegra/apply_binaries.sh``. MB1 Configuration Changes @@@@@@@@@@@@@@@@@@@@@@@@@ Multiple ``.cfg`` files define boot time configuration of the hardware. They are applied by Bootloader. The MB1 boot configuration tables are available at:: /bootloader/t186ref/BCT Pinmux Changes ############## If your board schematic differs from that for Jetson AGX Xavier Developer Kit board, you must change the pinmux configuration applied by the software. To define your board’s pinmux configuration, download the `Jetson AGX Xavier pinmux `__ table from the Jetson Download Center. Be sure to get the right version of the table for your SOM. The table contains a spreadsheet, and is provided to: - Show the locations and default pinmux settings - Define the pinmux settings in the source code or device tree You must customize the spreadsheet for the configuration of your board. Once done, you must convert the ``.dtsi`` file generated by Excel to a ``.cfg``. For instructions, see the README file at:: Linux_for_Tegra/kernel/pinmux/t19x/ You must perform the same conversion for ``gpio.dtsi`` and ``padvoltage.dtsi``. GPIO Changes ############ If you designed your own carrier board, to translate from SOM connector pins to actual GPIO numbers you must understand GPIO mapping formula below. The translated GPIO numbers can be controlled by the driver. For example, to check the GPIO number of ``SLVS_HSYNC``, perform the following steps. To check the GPIO number $$$$$$$$$$$$$$$$$$$$$$$$ #. Search for ``SLVS_HSYNC`` in the Jetson AGX Xavier pinmux table (see `Pinmux Changes`_). #. Confirm that the Customer Usage field is applied to ``GPIO3_PQ.04``. #. Search PQ.04 using the following command:: cat /sys/kernel/debug/gpio | grep PQ.04 4. For example Output:: gpio-xxx (PQ.04 ) 5. GPIO number of ``SLVS_HSYNC`` is xxx. Note: To use a pin as GPIO, make sure that E_IO_HV field is disabled in corresponding pinmux register of the GPIO pin. You can **disable** the field **3.3V Tolerance Enable** in pinmux spreadsheet and reflash the board with the updated pinmux file. PMIC Changes ############ The PMIC configuration file configures the initial PMIC in the P2888 SOM. Some GPIO expander-based GPIO regulator settings in the P2822 carrier board configurations are also defined. Review this configuration file to replace any references to the P2822 carrier board to your custom board. If required, include any regulator information to enable this file. For example, remove the following section that is writing to a slave on the I2C controller 0 address 0x74 in the P2822 carrier board. Additionally, update the number of blocks and array number for other entries in ``block:tegra194-mb1-bct-pmic-p2888-0001-a04-p2822-0000.cfg``:: # 5V0_HDMI_EN pmic.system.block[0].type = 1; #I2C pmic.system.block[0].controller-id = 4; pmic.system.block[0].slave-add = 0x78; # 7BIt:0x3c pmic.system.block[0].reg-data-size = 8; pmic.system.block[0].reg-add-size = 8; pmic.system.block[0].block-delay = 10; pmic.system.block[0].commands[0].0x53.0x38 = 0x00; #SD4 FPS UP slot 0 pmic.system.block[0].commands[1].0x55.0x38 = 0x10; #GPIO2 FPS UP slot 2 pmic.system.block[0].commands[2].0x41.0x1C = 0x1C; #SLPEN=1, CLRSE = 11 Enabling the WDT_RESET_OUT_N Pin for Watchdog Timeout ##################################################### To enable the ``WDT_RESET_OUT_N`` pin for watchdog timeout: 1. Confirm that the pinmux function of the ``WDT_RESET_OUT_N`` pin (``GPIO3_PQ.03``) is ``WDT_RESET_OUTA``. 2. Add a ``pmc_rst_req_cfg`` entry, e.g. ``"pmc_rst_req_cfg = 0x3"``, to ``Linux_for_tegra/bootloader/t186ref/BCT/tegra194-mb1-bct-misc-l4t.cfg``. ``pmc_rst_req_cfg`` configures ``WDT_RESET_OUT`` signal generation on watchdog expiry: - Bit 0: 1 = Toggle ``WDT_RESET_OUT`` on expiry of WDT. - Bit 1: 1 = Toggle ``WDT_RESET_OUT`` on expiry of AOWDT. - Bit 3: 1 = Toggle ``WDT_RESET_OUT`` on software-initiated reset. .. note:: When ``WDT_RESET_OUT`` signal generation is enabled, a reset caused by WDT/AOWDT/SW reset halts booting until ``RST_IN`` (external reset) is toggled. 3. Reflash the whole system or update only the ``MB1_BCT`` partition. Porting the Linux Kernel @@@@@@@@@@@@@@@@@@@@@@@@ It is assumed that you are using a P2888 SOM connected to a P2822 carrier board which have not been modified; the eMMC, PMIC, and DDR are the same with the same routing of lines. The modifications you are making are for the SOM and the carrier board. Consequently, based on the peripherals present on your carrier board, you can modify the ``.dts`` files by disabling/enabling the controllers and changing the supplies. To port the kernel configuration code (the device tree) to your platform, modify one of the distributed configuration files to describe the design of your platform. The configuration files are available at:: /hardware/nvidia/platform/t19x/ /hardware/nvidia/soc/t19x The final ``.dtb`` file used is: - For original Jetson AGX Xavier (16 OR 32\ |GB| RAM) or Jetson AGX Xavier 64GB (64\ |GB| RAM: ``tegra194-p2888-0001-p2822-0000.dtb`` - For Jetson AGX Xavier Industrial: ``tegra194-p2888-0008-p2822-0000.dtb`` By reading the above file, you can see which other ``.dtsi`` files are referenced by ``include`` statements. Common ``.dtsi`` files that may be modified to reflect hardware design changes include: +--------------------------------+----------------------------------------------------+ | Types of changes | DTSI filename or location | +================================+====================================================+ | Power supply changes | ``tegra194-power-tree-p2888-0001-p2822-1000.dtsi`` | +--------------------------------+----------------------------------------------------+ | Regulator parameter changes | ``tegra194-spmic-p2888-0001.dtsi`` | +--------------------------------+----------------------------------------------------+ | Display panel and node changes | For details, see the | | | :ref:`Display Configuration and Bringup | | | ` | | | section of the topic | | | :ref:`Kernel Customization | | | `. | +--------------------------------+----------------------------------------------------+ | ODM data based feature | ``tegra194-plugin-manager-p2888-0000.dtsi`` | | configuration | | +--------------------------------+----------------------------------------------------+ | NVIDIA SoC controller state to | ``soc/t19x/kernel-dts/tegra194-soc/`` | | enable/disable a controller | | +--------------------------------+----------------------------------------------------+ | Panels related ``.dts`` files | ``platform/tegra/common/kernel-dts/panels/`` | +--------------------------------+----------------------------------------------------+ Verify that no other ``.dts`` or ``.dtsi`` files, including these ``.dts`` files, override any changes you make. As a best practice, create your own set of ``.dts`` files based on the Jetson AGX Xavier files already present. Rename your newly created files to the name of your board. .. note:: Use ``fdtdump`` or ``dtc`` to generate a ``.dts`` from the final ``.dtb`` file and check whether your changes have taken effect. The command usage is:: $ dtc -I dtb -O dts tegra194-p2888-0001-p2822-0000.dtb > tegra194-p2888-0001-p2822-0000.dts $ fdtdump dts tegra194-p2888-0001-p2822-0000.dtb > tegra194-p2888-0001-p2822-0000.dts Where ```` is: - For the original Jetson AGX Xavier or Jetson AGX Xavier 64GB: ``tegra194-p2888-0001-p2822-0000`` - For Jetson AGX Xavier Industrial without Jetson safety extension package: ``tegra194-p2888-0008-p2822-0000`` - For Jetson AGX Xavier Industrial with Jetson safety extension package: ``tegra194-p2888-0008-p2822-0000-safejetpack`` This configuration is part of the Jetson Safety Extension Package, available on request. PCIe Controller Configuration @@@@@@@@@@@@@@@@@@@@@@@@@@@@@ The PCIe host controller is based on Synopsis Designware PCIe intellectual property, and thus inherits all the common properties defined in the information file at:: $(KERNEL_TOP)/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt PCIe Controller Features ######################## Jetson AGX Xavier series has six PCIe controllers with these specifications: - **Speed**: All controllers support up to Gen4 speed. - **Lane width**: - C0, C5: up to x8 - C4: up to x4 - C1, C2, C3: x1 - **Controllers**: Controllers C0, C4 and C5 support dual mode, that is, can be configured as endpoints. - **ASPM**: All controllers support ASPM. The Jetson AGX Xavier default PCIe configuration is: - C5: x8 - C0: x4 - C1, C3: x1 These PCIe slots available on the Jetson AGX Xavier series: - **M.2 Key M**: C0 controller operates in x4. Any M.2 Key M form factor NVMe cards can be connected. - **eSATA controller**: C1 controller operates in x1. The eSATA port is available to connect any SATA drive. - **M.2 Key E**: C3 controller operates in x1 mode. Any M.2 Key E form factor cards like Wi-Fi can be connected. - **PCIe slot**: C5 controller operates in x8 mode. Any PCIe card can be connected. The PCIe slot is of x16 size to connect x16 card, but operates in x8 mode. For information about Jetson AGX Xavier series-specific PCIe controller configuration, see the device tree documentation file at:: $(KERNEL_TOP)/Documentation/devicetree/bindings/pci/nvidia,tegra19x-pcie.txt This file covers topics that include configuring maximum link speed and link width, and advertisement of different ASPM states. To enable SMBus for PCIe slot $$$$$$$$$$$$$$$$$$$$$$$$$$$$$ In the file at:: $(TOP)/hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-p2888-0000-a00.dtsi Uncomment the following line:: /*&tegra_main_gpio TEGRA194_MAIN_GPIO(Y, 4) GPIO_ACTIVE_HIGH */ /* I2C*/ .. todo:: Vishruth commented, “Does not exist in the source file.” That implies that the instruction should be deleted, but perhaps a different file needs to be uncommented, or something else needs to be done. Please give me direct advice: delete “Uncomment…” and the line shown, or replace it with something else? Then flash a new DTB. Porting the Universal Serial Bus @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ The Jetson AGX Xavier series can support up to four enhanced SuperSpeed Universal Serial Bus (USB) ports. In some implementations, not all of these ports can be used because of UPHY lane sharing among PCIE, SATA, UFS, and XUSB. The Jetson P2822 carrier board is designed and verified for three USB3.1 ports. If you designed your own carrier board, verify the UPHY lane mapping and compatibility between P2822 and your custom board by consulting the NVIDIA team. USB Structure ############# An enhanced SuperSpeed USB port has nine pins: - VBUS - GND - D+ - D− - Two differential signal pairs for SuperSpeed data transfer - One ground (``GND_DRAIN``) for drain wire termination and managing EMI, RFI, and signal integrity .. figure:: JetsonAgxXavierSeries/UsbStructure.svg :alt: Enhanced Superspeed USB port pinout :figwidth: 240 px The D+/D− signal pins connect to UTMI pads. The SSTX/SSRX signal pins connect to UPHY and are handled by a single UPHY lane. As UPHY lanes are shared between PCIE, SATA, UFS, and XUSB, UPHY lanes must be assigned according to the custom carrier board’s requirements. UPHY Lane Assignment #################### UPHY is an acronym for **universal physical layer**, a physical I/O interface layer that can serve multiple types of interfaces, e.g. USB, PCIe, SATA, and UFS. A UPHY lane is a lane in UPHY which can support multiple types of interfaces. The Jetson P2822 carrier board is designed and verified for three USB3.1 ports. The verified use cases and their UPHY lane assignments are shown in the following two tables. .. raw:: html :file: JetsonAgxXavierSeries/UphyLaneAssignment.htm The Jetson AGX Xavier modules are designed to support the configurations listed in these tables. Released software also supports these configurations. For further information, refer to `NVIDIA Jetson AGX Xavier Technical Reference Manual `__ (TRM), and consult NVIDIA before designing your custom board. .. todo:: I can't get the J.D.C. to display a page with a search result specified in the URL, even by copying the URL from a page displayed manually. This used to work. Required Device Tree Changes ############################ This section provides guidance about checking schematics and configuring USB ports in the device tree. All the examples are based on the design of Jetson AGX Xavier P2822 carrier board. For a Host-Only Port $$$$$$$$$$$$$$$$$$$$ This section takes J513, a USB 3.1 type-C connector for example of a host-only port. Go Through the Schematics %%%%%%%%%%%%%%%%%%%%%%%%% .. note:: The P2822 carrier board’s schematic file, ``P2822_B02_Concept_schematics.pdf``, is included in `Jetson AGX Xavier Developer Kit Carrier Board Design Files `__. - Check the USB connectors on the P2822 carrier board and find the socket location wired to the P2888 SOM. USB2.0 signal pins D+/D- (``USB1_D*``) wire out from J513 and lead to C10 (``USB1_N``) and C11 (``USB1_P``) on the SOM socket. .. figure:: JetsonAgxXavierSeries/GoThroughTheSchematics(USB20).svg :alt: USB 2.0 pinout :figwidth: 400 px - USB3.1 differential signal pairs (``TX*`` and ``RX*``) wire out from J513 and lead to K16 (``UPHY_TX6_N``), K17 (``UPHY_TX6_P``), B16 (``UPHY_RX6_N``), and B17 (``UPHY_RX6_P``) on the SOM socket through U523, the USB type-C alt mode switch. .. figure:: JetsonAgxXavierSeries/GoThroughTheSchematics(USB31).svg :alt: USB 3.1 pinout :figwidth: 800 px Through the schematic, we can conclude that for J513: - The USB2.0 signal pair is wired to UTMI pad 1 (USB2 port 1). - The USB3.1 signal pairs are wired to UPHY lane 6 (USB3.1 port 0 according to UPHY lane mapping). The xusb_padctl Node %%%%%%%%%%%%%%%%%%%% The device tree’s xusb_padctl node follows the conventions of the ``pinctrl-bindings.txt`` kernel document. It contains two sets of groups named ``pads`` and ``ports``, which describe USB2 and USB3 signals along with parameters and port numbers. The name of each parameter description subnode in ``pads`` and ``ports`` must be in the form ``-``, where ```` is ``"usb2"`` or ``"usb3"`` and ```` is the associated port number. The pads Subnode ^^^^^^^^^^^^^^^^ - ``nvidia,function``: A string containing the name of the function to mux to the pin or group. Must be ``"xusb"``. The ports Subnode ^^^^^^^^^^^^^^^^^ - ``mode``: A string that describes USB port capability. A port for USB2 must have this property. It must be one of these values: - ``host`` - ``peripheral`` - ``otg`` - ``nvidia,usb2-companion``: USB2 port (0, 1, 2, or 3) to which the port is mapped. A port for USB3 must have this property. - ``nvidia,oc-pin``: The overcurrent VBUS pin the port is using. The value must be positive or zero. .. note:: Overcurrent detection and handling for J512 and J513 on the P2822 carrier board are controlled by U513, a Cypress Type-C controller. Therefore, you need not set this property for J512 and J513 USB ports. - ``vbus-supply``: VBUS regulator for the corresponding UTMI pad. Set to ``&battery_reg`` for a dummy regulator. .. note:: The VBUS regulators for J512 and J513 are controlled by U513, a Cypress Type-C controller. Therefore, you must set dummy regulators for those ports on the P2822 carrier board. - ``nvidia,usb3-gen1-only``: A number (1/0) which describes whether or not to limit the port speed to USB3.1 gen1. .. note:: J507, an eSATA port on the P2822 carrier board, only supports USB3.1 gen1 speed. Therefore, you must set ``nvidia,usb3-gen1-only`` 1 (true) for 507. For the detailed information about ``xusb_padctl``, see the documentation at:: kernel/kernel-5.10/Documentation/devicetree/bindings/phy/nvidia,xusb-padctl.txt Take J513 (USB3.1 type-C connector) for example. Create a pad/port node and property list for J513 based on the device tree structure described above:: xusb_padctl: xusb_padctl@3520000 { ... pads { usb2 { lanes { usb2-1 { nvidia,function = "xusb"; status = "okay"; }; ... }; }; usb3 { lanes { ... usb3-0 { nvidia,function = "xusb"; status = "okay"; }; ... }; }; }; ports { usb2-1 { mode = "host"; vbus-supply = <&battery_reg>; status = "okay"; }; ... usb3-0 { nvidia,usb2-companion = <1>; status = "okay"; }; ... }; }; .. _HR.JetsonModuleAdaptationAndBringUp.JetsonAgxXavierSeries-PortingTheLinuxKernel.RequiredDeviceTreeChanges.ForAHostOnlyPort.UnderTheXhciNode: Under the xHCI Node %%%%%%%%%%%%%%%%%%% The Jetson AGX Xavier xHCI controller complies to xHCI specifications, which support both USB 2.0 HighSpeed/FullSpeed/LowSpeed and USB 3.1 SuperSpeed protocols. - ``phys``: Must contain an entry for each entry in ``phy-names``. - ``phy-names``: Must include an entry for each PHY used by the controller. Names must be in the form ``-``, where ```` is ``usb2`` or ``usb3``. - ``nvidia,xusb-padctl``: A pointer to the ``xusb-padctl`` node. For detailed information about xHCI, see the documentation at:: kernel/kernel-5.10/Documentation/devicetree/bindings/usb/nvidia,tegra-xhci.txt Take J513 USB3.1 type-C connector, for example. Create an xHCI node and property list for J513 based on the device tree structure described above:: tegra_xhci: xhci@3610000 { ... phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-1}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-0}>; phy-names = "usb2-1", "usb3-0"; nvidia,xusb-padctl = <&xusb_padctl>; status = "okay"; ... }; For an OTG (On-The-GO) Port $$$$$$$$$$$$$$$$$$$$$$$$$$$ USB On-The-Go, often abbreviated **USB OTG** or just **OTG**, is a specification that allows USB to act as a host or a device in the same port. A USB OTG port can switch back and forth between the roles of host and device. This section takes J512, USB3.1 type-C connector, as an example of an OTG port. An OTG port adds a fifth pin to the standard USB connector, called the **ID pin**. An OTG cable has an A-plug on one end and a B-plug on the other end. The A-plug’s ID pin is grounded, while the B-plug’s ID pin is floating. A device with an A-plug inserted becomes and OTG A-device (host), and a device with a B-plug inserted becomes a B-device (device). .. figure:: JetsonAgxXavierSeries/ForAnOtgOnTheGoPort.svg :alt: On-The-Go (OTG) port pinout :figwidth: 240 px .. todo:: Looking more carefully at this drawing than I have before, I have some questions. Don't the wider-than-high rectangles in the center represent the actual contacts on the connector? If so, it's confusing to put the 1...10 numbers on lines coming out of the left side, where they appear to refer to conductors coming out the side of the base. The numbers should be next to the contacts, and the lines shouldn't be there at all. Also, I compared this diagram to the carrier board diagrams in the "Hardware Setup" topic, and I didn't see anything there that remotely resembles the connector shown here. Nor is there a connector on the carrier board diagrams labeled anything like "USB3.0 Micro AB." There are USB Type A connectors, USB Micro B connectors, and USB Type C connectors. One of these diagrams is inaccurate. .. note:: The roles of J512, the port switch, between the host driver (xHCI) and device driver (xUDC) are controlled by a U513 Cypress Type-C controller and ``ucsi_ccg`` driver in Jetson AGX Xavier Developer Kit. Go Through the Schematics %%%%%%%%%%%%%%%%%%%%%%%%% .. note:: The P2822 carrier board’s schematic file, ``P2822_B02_Concept_schematics.pdf``, is included in `Jetson AGX Xavier Developer Kit Carrier Board Design Files `__. Check the USB connectors on the P2822 carrier board and find the wired socket location to P2888. .. todo:: While minimizing references to part numbers (Winnie’s request of 9/25/2019) I found this sentence and realized that it doesn't make sense. Can you clarify, please? - USB2.0 signal pins D+/D− (``USB0_D*``) wire out from J512 and lead to F12 (``USB0_P``) and F13 (``USB0_N``) on the SOM socket. .. figure:: JetsonAgxXavierSeries/GoThroughTheSchematics(2).svg :alt: USB 2.0 signal pin connections :figwidth: 480 px - USB3.1 differential signal pairs (``TX*`` and ``RX*``) wire out from J512 and lead to G22 (``UPHY_TX1_N``), G23 (``UPHY_TX1_P``), C22 (``UPHY_RX1_N``), and C23 (``UPHY_RX1_P``) on the SOM socket through U522, the USB type-C alt mode switch. .. figure:: JetsonAgxXavierSeries/GoThroughTheSchematics(3).svg :alt: USB 3.1 signal pin connections :figwidth: 800 px Through the schematic, you can see that for J513: - USB2.0 signal pair is wired to UTMI pad 0 (USB2 port 0). - USB3.1 signal pairs are wired to UPHY lane 1 (USB3.1 port 2 according to UPHY lane mapping). The USB Connector Class %%%%%%%%%%%%%%%%%%%%%%% A USB connector class represents a physical USB connector. It should be the child of a USB interface controller or a separate node when it is attached to the MUX and USB interface controllers. Generally, port switching between the roles of an OTG port is controlled by the host driver (xHCI) and device driver (xUDC), and can be defined by the state of the ID pin and the ``VBUS_DETECT`` pin. Taking GPIO_M3 as the ``VBUS_DETECT`` pin and ``GPIO_Q0`` as the ID pin, for example: 1. Find the corresponding GPIO states on the ``VBUS_DETECT`` pin and ID pin. Generally, the ID pin is designed as internal pull high (logical high). With an A-plug connected the ID pin is pulled to ground (logical low), while with a B-plug connected or no cable connected it remains logical high. The operation of the ``VBUS_DETECT`` pin depends on the device’s design. Consider the schematic in the following diagram, for example: .. figure:: JetsonAgxXavierSeries/Extcon.svg :alt: Example of VBUS_DETECT pin connection :figwidth: 650 px With a B-plug connected ``VBUS_DETECT`` is logical low, because ``VBUS`` is provided from an external power supply, and when no cable is connected it is logical high. .. note:: ``VBUS_DETECT`` is initially logical high, then logical low because VBUS is provided by the host controller. Therefore, the state of the ``VBUS_DETECT`` pin does not matter when the OTG port is operating in host mode. 2. Create the table of GPIO states and their corresponding output cable states: ============ =============== ===================== GPIO_Q0 (ID) GPIO_M3 EXTCON_STATE (VBUS_DETECT) ============ =============== ===================== 1 1 Not Connected ------------ --------------- --------------------- 0 0 HOST ------------ --------------- --------------------- 0 1 HOST ------------ --------------- --------------------- 1 0 DEVICE ============ =============== ===================== Under the Connector Node (Not Used on the P2822 Carrier Board) %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% Port switching between the roles of an OTG port is defined by the state of the ID pin and the ``VBUS_DETECT`` pin and the settings of the USB connector class. - ``compatible``: Value must be ``"gpio-usb-b-connector"``. - ``label``: Symbolic name for the connector - ``type``: Size of the connector, should be specified in case of non-full size 'usb-a-connector' or 'usb-b-connector' compatible connectors. - ``id-gpios``: An input gpio for USB ID pin. - ``vbus-gpios``: An input gpio for the USB VBus pin, used to detect the presence of VBUS 5V. - ``cable-connected-on-boot``: Name of the output cable that is connected at boot time. It be ``USB_ROLE_NONE``, ``USB_ROLE_HOST``, or ``USB_ROLE_DEVICE``. If not specified, the system assumes that no cable will be connected. - wakeup-source: A Boolean, and ``true`` if the device can wake up the system. For the detailed information about the ``USBConnectorClass``, see the documentation at:: kernel/kernel-5.10/Documentation/devicetree/bindings/connector/usb-connector.yaml .. note:: OTG port switching between the host driver (xHCI) and device driver (xUDC) roles are controlled by the Cypress Type-C controller. Therefore, this section is not a part of the device-tree for the Jetson AGX Xavier Developer Kit. - Create a ``USBConnectorClass`` device node and property list based on the device tree structure described above and the table of GPIO states and corresponding output cable states for ``GPIO_Q0`` and ``GPIO_M3``:: xvusb_padctl: xusb_padctl@3520000 { .... ports { usb2-0 { ... Connector { compatible = "gpio-usb-b-connector"; label = "micro-USB"; type = "micro"; vbus-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(M, 3) GPIO_ACTIVE_LOW>; id-gpio = <&tegra_main_gpio TEGRA194_MAIN_GPIO(Q, 0) GPIO_ACTIVE_HIGH>; }; ... }; }; ...; For the example of ``USBConnectorClass``, see the device tree's source code at:: ``hardware/nvidia/platform/t19x/galen/kernel-dts/common/tegra194-e3366-1199-a00.dtsi`` .. note:: Check the pinmux table for the GPIO that corresponds to the ID pin and ``VBUS_DETECT`` pin. Under the ucsi_ccg Node %%%%%%%%%%%%%%%%%%%%%%% In the Jetson AGX Xavier Developer Kit role, switching port J512 between the host driver (xHCI) and the device driver (xUDC) modes is controlled by default by U513, a Cypress Type-C controller, and the ``ucsi_ccg`` driver. - ``compatible``: Value must be ``"nvidia,ccgx-ucsi"``. - ``ccgx,firmware-build``: The ccg firmware builder. - ``reg``: The i2c slave address of typec port controller device. - ``interrupt-parent``: The phandle to the interrupt controller which provides the interrupt. - ``interrupts``: The interrupt specification for CCGx's notification. - ``connector``: The ``"usb-c-connector"`` that is attached to the CCGx chip, and the bindings of the connector node are specified in: ``Documentation/devicetree/bindings/connector/usb-connector.yaml``. For detailed information about ``ucsi_ccg``, refer to the driver source code at:: kernel/kernel-5.10/driver/usb/typec/ucsi/ucsi_ccg.c Taking J512 USB3.1 type-C connector as an example, create a ``ucsi_ccg`` node and property list based on the device tree structure described above for J512:: ucsi_ccg: ucsi_ccg@8 { status = "okay"; compatible = "nvidia,ccgx-ucsi"; ccgx,firmware-build = "gn"; reg = <0x08>; interrupt-parent = <&tegra_aon_gpio>; interrupts = ; ccg_typec_con0: connector@0 { compatible = "usb-c-connector"; label = "USB-C"; data-role = "dual"; port { ucsi_ccg_p0: endpoint { remote-endpoint = <&usb_role_switch0>; }; }; }; Under the xusb_padctl Node %%%%%%%%%%%%%%%%%%%%%%%%%% ``xusb_padctl`` settings for an OTG port are the same as for a host-only port except that the mode should be ``otg``, the ``usb-role-switch`` property is added, and the remote endpoint settings are attached to the CCGx chip, and the bindings of connector node are specified in the ``Documentation/devicetree/bindings/connector/usb-connector.yaml`` file. Taking J512, the USB3.1 type-C connector, as an example, create a pad/port node and property list:: xusb_padctl: xusb_padctl@3520000 { ... pads { usb2 { lanes { usb2-0 { nvidia,function = "xusb"; status = "okay"; }; ... }; }; usb3 { lanes { ... usb3-2 { nvidia,function = "xusb"; status = "okay"; }; ... }; }; }; ports { usb2-0 { mode = "otg"; usb-role-switch vbus-supply = <&battery_reg>; status = "okay"; port { usb_role_switch0: endpoint { remote-endpoint = <&ccg_typec_con0>; }; }; }; ... usb3-2 { nvidia,usb2-companion = <0>; status = "okay"; }; ... }; }; Under the xHCI Node %%%%%%%%%%%%%%%%%%% The xHCI settings for an OTG port are the same as for a host-only port. Taking J512, the USB3.1 type-C connector, as an example, create an xHCI node and property list based on the device tree structure described in :ref:`For a Host-Only Port, Under the xHCI Node ` for a host-only port:: tegra_xhci: xhci@3610000 { ... phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>; phy-names = "usb2-0", "usb3-2"; nvidia,xusb-padctl = <&xusb_padctl>; status = "okay"; ... }; Under the xUDC Node %%%%%%%%%%%%%%%%%%% The Jetson AGX Xavier xUDC controller supports both USB 2.0 HighSpeed/FullSpeed and USB 3.1 SuperSpeed protocols. - ``charger-detector``: USB charger detection support. Must be the ``phandle`` of the USB charger detection driver DT node. - ``phys``: An array; must contain a pointer to the node that defines each PHY in ``phy-names``. - ``phy-names``: An array; must contain an entry for each PHY used by the controller. Names must be in the form ``-``, where ```` is ``"usb2"`` or ``"usb3"``. - ``nvidia,xusb-padctl``: Must be a pointer to the ``xusb-padctl`` node. For detailed information about xUDC, see the documentation at:: kernel/kernel-5.10/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.txt Taking J512, the USB3.1 type-C connector, as an example, create an xUDC node and property list for J512 based on the device tree structure described above:: tegra_xudc: xudc@3550000 { phys = <&{/xusb_padctl@3520000/pads/usb2/lanes/usb2-0}>, <&{/xusb_padctl@3520000/pads/usb3/lanes/usb3-2}>; phy-names = "usb2-0", "usb3-2"; nvidia,xusb-padctl = <&xusb_padctl>; status = "okay"; }; .. note:: Before you design your custom board, verify the lane mapping against the `Jetson AGX Xavier Series OEM Product Design Guide `_. Flashing the Build Image @@@@@@@@@@@@@@@@@@@@@@@@ When flashing the build image, use your specific board name. The flashing script uses the configuration in the ``.conf`` file during the flashing process. Setting Optional Environment Variables ###################################### The ``flash.sh`` script updates the following environment variables based on board EEPROM and other parameters passed. If you want to give specific values to these variables, define them in the board-specific file board.conf to override the default values. :: # Optional Environment Variables: # BCTFILE ---------------- Boot control table configuration file to be used. # BOARDID ---------------- Pass boardid to override EEPROM value # BOARDREV --------------- Pass board_revision to override EEPROM value # BOARDSKU --------------- Pass board_sku to override EEPROM value # BOOTLOADER ------------- Bootloader binary to be flashed # BOOTPARTLIMIT ---------- GPT data limit. (== Max BCT size + PPT size) # BOOTPARTSIZE ----------- Total eMMC HW boot partition size. # CFGFILE ---------------- Partition table configuration file to be used. # CMDLINE ---------------- Target cmdline. See help for more information. # DEVSECTSIZE ------------ Device Sector size. (default = 512Byte). # DTBFILE ---------------- Device Tree file to be used. # EMMCSIZE --------------- Size of target device eMMC (boot0+boot1+user). # FLASHAPP --------------- Flash application running in host machine. # FLASHER ---------------- Flash server running in target machine. # INITRD ----------------- Initrd image file to be flashed. # KERNEL_IMAGE ----------- Linux kernel zImage file to be flashed. # MTS -------------------- MTS file name such as mts_si. # MTSPREBOOT ------------- MTS preboot file name such as mts_preboot_si. # NFSARGS ---------------- Static Network assignments. # ::: # NFSROOT ---------------- NFSROOT i.e. :/exported/rootfs_dir. # ODMDATA ---------------- Odmdata to be used. # PKCKEY ----------------- RSA key file to use to sign bootloader images. # ROOTFSSIZE ------------- Linux RootFS size (internal emmc/nand only). # ROOTFS_DIR ------------- Linux RootFS directory name. # SBKKEY ----------------- SBK key file to use to encrypt bootloader images. # SCEFILE ---------------- SCE firmware file such as camera-rcpu-sce.img. # SPEFILE ---------------- SPE firmware file path such as bootloader/spe.bin. # FAB -------------------- Target board's FAB ID. # TEGRABOOT -------------- Lower layer bootloader such as nvtboot.bin. # WB0BOOT ---------------- Warmboot code such as nvtbootwb0.bin .. note:: All the parameters must be added below the reference to the ``.conf.common`` file to be reflected in the flashed image. Here is an example of environment variable settings:: source "${LDK_DIR}/p2972-0000.conf.common"; PINMUX_CONFIG="tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg"; BPFDTB_FILE=tegra194-a02-bpmp-p2888-as-galen-8gb.dtb; DTB_FILE=tegra194-p2888-0006-p2822-0000.dtb; TBCDTB_FILE=tegra194-p2888-0006-p2822-0000.dtb; EMMC_BCT="tegra194-mb1-bct-memcfg-p2888-0006.cfg"; MISC_COLD_BOOT_CONFIG="tegra194-mb1-bct-misc-l4t-p2888-0006.cfg"; To flash the build image ######################## - Execute the following command:: $ sudo ./flash.sh mmcblk0p1