.. _SD.Bootloader.MiscConfig: .. include:: /content/swdocs.rsts .. spelling:: AO AON apb axi AST BootROM Boolean BR BCT dts carveout CBB coldboot CPU DIVN CFG BL tegrabct tegrabct_v2 Mem MB1 MB2 MC OEM FW SW VF HSM SC7 SC8 Watchdog PMIC OTP L1 L2 addr Ao AoBlock aoblock aotag hsm preinstalled sc vfsensor SPE spe FW DRAM ECC ecc SC7 McVideoProtectSizeMb McVideoProtect WriteAccess VPR TZ RAMDUMP TZDRAM GSC SHA CTX PLLAON BPMP SE CBB SC7 MSS CLK CAN2 BPMP McVideoProtectSizeMb McVideoProtect WriteAccess osc va MTS uCode CAN1 CAN2 DCLS TCM l1 tz DIVISOR DIVN SDRAM RCM misc SMMU MMU DIVP CORESIGHT CTL pllx PLLX WDT CCPLEX NAFLL CFG1 CFG2 CFG3 FMON vrefRO VrefRO calib OSC uart checkSum nv3p pmc vmon avfs adc lut vfgain ndiv coeff nafll mdiv pdiv fll frug ldmem divm waypoint vsense0 cg aotag ccplex avfs adc cpubl ape apr sce rce NVDEC WPR1 WPR2 TSECA TSECB CPUTZ TSEC PFSD VPR vpr mss se ctx tz mb bpmp apb axi cbb se aon nic aon osc pllaon divn divm divp frac va spe fw rcm RCM gsc mts MTS uCode vpr tzdram ecc gsc os Coresight ctl csite mc wr etr ccplex avfs nafll fll init Fll Init ldmem Ldmem lut sw req ndiv vfgain coeff pdiv frug adc vmon pllx aocluster evp alloc se oem uart usb nvjtag swd sel wdt th boolean bootchain tegrashell IST dGPU vrefRO calib osc pmc bct mem configs MSS recom vpr dgpu !!!!!!!!!!!!!!!!!!!!!!!!!!!!! Miscellaneous Configuration !!!!!!!!!!!!!!!!!!!!!!!!!!!!! The different settings that do not fit into the other categories are documented in miscellaneous configuration file. MB1 Feature Fields @@@@@@@@@@@@@@@@@@ These features are Boolean flags that enable or disable functionality in MB1: .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - disable_spe - Here are the values: - 0: Disables load of SPE-FW by MB1. - 1: Enables load of SPE-FW by MB1. * - enable_dram_page_blacklisting - Here are the values: - 0: Disables DRAM ECC page blacklisting feature. - 1: Enables DRAM ECC page blacklisting feature. * - disable_sc7 - Here are the values: - 0: Enables SC7-entry/exit support. - 1: Enables SC7-entry/exit support. * - disable_fuse_visibility - Certain fuses cannot be read or written by default because they are not visible. - 0: Keeps the default visibility of fuses. - 1: Enables visibility of such fuses. * - enable_vpr_resize - Here are the values: - 0: VPR is allocated based on the **McVideoProtectSizeMb**, **McVideoProtect**, and **WriteAccess** fields of the SDRAM config file. - 1: VPR-resize feature is enabled. For example, no VPR carveout is allocated by MB1 and TZ write access to VPR carveout is enabled. * - l2_mss_encrypt_regeneration - Here are the values: - On L2 RAMDUMP reset, regenerate MSS encryption keys for the carveouts. This is a bit-field with the following bit-mapping: - 1:TZDRAM - 2:VPR - 3:GSC * - se_ctx_save_tz_lock - Restrict SE context save and SHA_CTX_INTEGRITY operation to TZ. * - disable_mb2_glitch_protection - Disable checks on DCLS faults, TCM parity error, TCM and cache ECC. * - enable_dram_error_injection - Here are the values: - 0: Disable DRAM error injection tests - 1: Enable DRAM error injection tests * - enable_dram_staged_scrubbing - Here are the values: - 0: If DRAM ECC is enabled, scrub entire DRAM - 1: If DRAM ECC is enabled, scrub DRAM in stages - each BL responsible for the DRAM portions that it uses. * - wait_for_debugger_connection - Here is the value: - 0: Do not wait for debugger connection at end of MB1. * - limit_l1_boot_client_freq - Here are the values: - 1: Spin in a while(1) loop at end of MB1 for debugger connection. - 0: Keep boot client frequencies (BPMP, SE, CBB, etc) same for L0 and L1 reset. Clock Data @@@@@@@@@@ The following fields allow certain clock-related customization. .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - bpmp_cpu_nic_divider - Controls the BPMP CPU frequency. - 0: Skip programming CLK_SOURCE_BPMP_CPU_NIC[BPMP_CPU_NIC_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_BPMP_CPU_NIC[BPM_CPU_NIC_CLK_DIVISOR]. * - bpmp_apb_divider - Controls the BPMP APB frequency. - 0: Skip programming of CLK_SOURCE_BPMP_APB[BPMP_APB_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_BPMP_APB[BPMP_APB_CLK_DIVISOR]. * - axi_cbb_divider - Controls the control backbone (CBB) frequency. - 0: Skip programming of CLK_SOURCE_AXI_CBB[AXI_CBB_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_AXI_CBB[AXI_CBB_CL_K_DIVISOR]. * - se_divider - Controls the SE (security engine) frequency. - 0: Skip programming of CLK_SOURCE_SE[SE_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_SE[SE_CLK_DIVISOR]. * - aon_cpu_nic_divider - Controls the AON/SPE CPU frequency. - 0: Skip programming of CLK_SOURCE_AON_CPU_NIC[AON_CPU_NIC_CLK_DIVISOR]. - on-zero: 1 + Value to be programmed in CLK_SOURCE_AON_CPU_NIC[AON_C←PU_NIC_CLK_DIVISOR]. * - aon_apb_divider - Controls the AON APB frequency. - 0: Skip programming of CLK_SOURCE_AON_CPU_NIC[AON_CPU_NIC_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_AON_CPU_NIC[AON_C←PU_NIC_CLK_DIVISOR]. * - aon_can0_divider - Controls the AON CAN1 frequency. - 0: Skip programming of CLK_SOURCE_CAN1[CAN1_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_CAN1[CAN1_CLK_DIVISOR]. * - aon_can1_divider - Controls the AON CAN2 frequency. - 0: Skip programming of CLK_SOURCE_CAN2[CAN2_CLK_DIVISOR]. - non-zero: 1 + Value to be programmed in CLK_SOURCE_CAN2[CAN2_CLK_DIVISOR]. * - osc_drive_strength - Oscillator drive strength. * - pllaon_divn - DIVN value of PLLAON. - 0: Use PLLAON_DIVN = 30, PLLAON_DIVM = 1, PLLAON_DIVP = 2. - non-zero: 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVN]. * - pllaon_divm - DIVN value of PLLAON. - DIVM value of PLLAON (ignored when clock.pllaon_divn = 0). - 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVM]. * - pllaon_divp - DIVN value of PLLAON. - DIVP value of PLLAON (ignored when clock.pllaon_divn = 0). - 1 + Value to be programmed in PLLAON_BASE[PLLAON_DIVP]. * - pllaon_divn_frac - Value to be programmed. AST Data @@@@@@@@ MB1/MB2 uses AST (address-translation) module for mapping the DRAM carveout for different firmwares into the 32-bit virtual address-space of the various auxiliary processor clusters. MB1 AST Data ############ .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - mb2_va - Virtual address for MB2 carveout in BPMP-R5 address-space. * - spe_fw_va - Virtual address for SPE-FW carveout in AON-R5 address-space. * - misc_carveout_va - Virtual address for MISC carveout in SCE-R5 address-space. * - rcm_blob_carveout_va - Virtual address for RCM-blob carveout in SCE-R5 address-space. * - temp_map_a_carveout_va - Virtual address for temporary mapping A used while loading binaries. * - temp_map_a_carveout_size - Size for temporary mapping A used while loading binaries. * - temp_map_a_carveout_va - Virtual address for temporary mapping B used while loading binaries. * - temp_map_a_carveout_size - Size for temporary mapping B used while loading binaries. .. note:: Here is some additional information: - None of the VA spaces above should overlap with an MMIO region or with each other. - Size fields should be power of 2. - VA fields should be aligned to their mapping/carveouts. Carveout Configuration @@@@@@@@@@@@@@@@@@@@@@ Although SDRAM Configuration has MC carveout's preferred base, size and permissions, it does not have the information that is required to allocate the carveouts by MB1. This information is specified by using the miscellaneous configuration file. For carveouts that are not protected by MC, all information (including size and preferred base address) is specified using miscellaneous configuration file. Each MC carveout configuration parameter has the following form: .. code-block:: none /{ misc { carveout { ; }; }; }; }; where: - ``carveout-type`` identifies the carveout and is one of the following: .. list-table:: :widths: auto :header-rows: 1 * - carveout-type - Description * - gsc@[1-31] - GSC carveout for various purposes. * - mts - MTS/CPU-uCode carveout. * - vpr - VPR carveout. * - tzdram - TZDRAM carveout used for SecureOS. * - os - OS carveout used for loading OS kernel. * - rcm - RCM carveout used for loading RCM-blob during RCM mode (temporary boot carveout). - ```` is one of the following: .. list-table:: :widths: auto :header-rows: 1 * - Parameter - Description * - pref_base - Preferred base address of carveout. * - size - Size of carveout (in bytes). * - alignment - Alignment of base address of carveout (in bytes). * - ecc_protected - When DRAM region-based ECC is enabled and there are non-ECC protected DR←AM regions, whether to allocate the carveout from ECC protected region. - 0: Allocate from non ECC protected region - 1: Allocate from ECC protected region * - bad_page_tolerant - When DRAM page blacklisting is enabled, whether it is OK to have bad pages in the carveout (only possible for very large carveouts and which are handled completely by component that can avoid bad pages using SMMU/MMU). - 0: No bad pages allowed for the carveout. - 1: Bad pages allowed for the carveout (allocation can be done without filtering bad pages). The valid combination of the carveouts and their parameters are specified in following table: .. list-table:: :widths: auto :header-rows: 1 * - Supported carveout-type - pref_base - size - alignment - ecc_protected - bad_page_tolerant * - gsc-[1-31]/mts/vpr - N/A - N/A - Yes - Yes - Yes * - tzdram/mb2/cpubl/misc/os/rcm - Yes - Yes - Yes - Yes - Yes Coresight Data ############## .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - cfg_system_ctl - Value to be programmed to CORESIGHT_CFG_SYSTEM_CTL. * - cfg_csite_mc_wr_ctrl - Value to be programmed to CORESIGHT_CFG_CSITE_MC_WR_CTRL. * - cfg_csite_mc_rd_ctrl - Value to be programmed to CORESIGHT_CFG_CSITE_MC_RD_CTRL. * - cfg_etr_mc_wr_ctrl - Value to be programmed to CORESIGHT_CFG_ETR_MC_WR_CTRL. * - cfg_etr_mc_rd_ctrl - Value to be programmed to CORESIGHT_CFG_ETR_MC_RD_CTRL. * - cfg_csite_cbb_wr_ctrl - Value to be programmed to CORESIGHT_CFG_CSITE_CBB_WR_CTRL. * - cfg_csite_cbb_rd_ctrl - Value to be programmed to CORESIGHT_CFG_CSITE_CBB_RD_CTRL. Firmware Load and Entry Configuration @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ The firmware configuration is specified as follows: .. code-block:: none /{ misc { ... ... firmware { { = ; }; }; }; }; where ```` is one of the mb2 or tzdram-e13 and is specified in the following table: .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - load-offset - Offset in the carveout where binary is loaded. * - entry-offset - Offset of the entry point in carveout. CPU Configuration @@@@@@@@@@@@@@@@@ .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - ccplex_platform_features - CPU platform features (should be 0). * - clock_mode.clock_burst_policy - CCPLEX clock burst policy. * - clock_mode.max_avfs_mode - Highest CCPLEX AVFS mode * - nafll_cfg2/fll_init - CCPLEX NAFLL CFG2 [Fll Init] * - nafll_cfg2/fll_ldmem - CCPLEX NAFLL CFG2 [Fll Ldmem] * - nafll_cfg2/fll_switch_ldmem - CCPLEX NAFLL CFG2 [Fll Switch Ldmem] * - nafll_cfg3 - CCPLEX NAFLL CFG3 * - nafll_ctrl1 - CCPLEX NAFLL CTRL1 * - nafll_ctrl2 - CCPLEX NAFLL CTRL2 * - lut_sw_freq_req/sw_override_ndiv - SW override for CCPLEX LUT frequency request * - lut_sw_freq_req/ndiv - NDIV for CCPLEX LUT frequency request * - lut_sw_freq_req/vfgain - VFGAIN for CCPLEX LUT frequency request * - lut_sw_freq_req/sw_override_vfgain - VFGAIN override for CCPLEX LUT frequency request * - nafll_coeff/mdiv - MDIV for NAFLL coefficient * - nafll_coeff/pdiv - PDIV for NAFLL coefficient * - nafll_coeff/fll_frug_main - FLL frug main for NAFLL coefficient * - nafll_coeff/fll_frug_fast - FLL frug fast for NAFLL coefficient * - adc_vmon.enable - Enable CCPLEX ADC voltage monitor * - min_adc_fuse_rev - Minimum ADC fuse revision * - pllx_base/divm - PLLX DIVM * - pllx_base/divn - PLLX DIVN * - pllx_base/divp - PLLX DIVP * - pllx_base/enable - Enable PLLX * - pllx_base/bypass - PLLX Bypass Enable Other Configuration @@@@@@@@@@@@@@@@@@@ .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - aocluster.evp_reset_addr - AON/SPE reset vector (in SPE BTCM). * - carveout_alloc_direction - Carveout allocation direction. - 0: End of DRAM - 1: End of 2GB DRAM (32b address space) - 2: Start of DRAM * - se_oem_group - Value to be programmed to SE0_OEM_GROUP_0/SE_RNG1_RNG1_OEM_GROUP_0. - (NVHS / NVLS / Lock bits are forced set) * - i2c-freq - List of < where, I2C controller instance has valid values 0 to 8. MB1 Soft Fuse Configurations ############################ There are certain platform-specific configurations or decisions in MB1 that are required from the early stages of MB1 even before storage is initialized and MB1-BCT is read (for example, debug port details, certain boot-mode controls, behavior in case of failure, and so on.). To address this requirement, an array of 64 fields is added to signed section of BR-BCT, which is opaque to BR but is consumed by MB1. In recovery mode, BR does not read BR-BCT, so this array is kept part of RCM message and is copied by BR to the same location where BR will have kept it in coldboot as part of BR-BCT. This array is called MB1 software fuses (soft-fuse). Debug Controls ############## .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - verbosity - Controls verbosity of debug logs on UART (verbosity increases with increasing value). - 0: UART logs disabled - 1: Critical prints only - 2: Error - 3: Warn - 4: Info - 5: Debug * - uart_instance - UART controller number where debug logs are spewed. - 0: UARTA (only for simulation platforms) - 2: UARTC (open-box debug) - 5: UARTF (closed-box debug, USB-Type C over DP_AUX pins) - 7: UARTH (closed-box debug, USB-Type C over USB-OTG * - usb_2_nvjtag - On-chip controller connected to the USB2 pins. - 0: ARMJTAG - 1: NVJTAG * - swd_usb_port_sel - USB2 port over which SWD should be configured. - 0: USB2 Port0 - 1: USB2 Port1 * - uart8_usb_port_sel - USB2 port over which UART should be configured. - 0: USB2 Port0 - 1: USB2 Port1 * - wdt_enable - Enable BPMP WDT 5th-expiry during the execution of MB1/MB2 (boolean). * - wdt_period_secs - BPMP WDT time period (in secs) per expiry. Boot Failure Controls ##################### .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - switch_bootchain - Switch boot chain in case of failure (boolean). * - reset_to_recovery - Trigger L1 RCM reset on failure (boolean). * - bootchain_switch_mechanism - Used if switch_bootchain is set to 1. - 0: Use BR-based boot-chain switching. - 1: Use Android A/B based boot-chain switching. * - bootchain_retry_count - Maximum number of retries for a single boot-chain (0-15). On/Off IST Mode Controls ######################## .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - platform_detection_flow - In RCM mode, enter platform detection flow (boolean). * - enable_tegrashell - In RCM mode, enter tegrashell mode (allowed only if FUSE_SECURITY_MODE_0 is not blown) (boolean). * - enable_IST - Enable Key On/Off IST boot (boolean). * - enable_LO_IST - Enable Key ON (L0) IST boot mode (boolean). - Used only if EnableIST is set to 1. * - enable_dgpu_IST - Enable dGPU IST during IST boot modes (boolean). Frequency Monitor Controls ########################## .. list-table:: :widths: auto :header-rows: 1 * - Field - Description * - vrefRO_calib_override - Override VrefRO Calibration Override based on SoftFuse instead of fuse (boolean). * - vrefRO_min_rev_threshold - Program VrefRO frequency adjustment target based on FUSE_VREF_CALIB_0 if (FUSE_ECO_RESERVE_1[3:0] > vrefRO_min_rev_threshold) (Used if vrefRO_calib_override is set to 0). * - vrefRO_calib_val - VrefRO Calibration Value used to program VrefRO frequency adjustment target (Used if vrefRO_calib_override is set to 1). * - osc_threshold_low - Lower Threshold of the FMON counter for OSC clock * - osc_threshold_high - Upper Threshold of the FMON counter for OSC clock. * - pmc_threshold_low - Lower Threshold of the FMON counter for 32K clock. * - pmc_threshold_high - Upper Threshold of the FMON counter for 32K clock. The miscellaneous configuration files are in the bct/t23x/misc/ directory. Here is a DTS example of the new miscellaneous configuration file: .. code-block:: none /dts-v1/; /{ misc { disable_spe = <0>; enable_vpr_resize = <0>; disable_sc7 = <1>; disable_fuse_visibility = <0>; disable_mb2_glitch_protection = <0>; carveout_alloc_direction = <2>; //Specify i2c bus speed in KHz i2c_freqency = <4 918>; // Soft fuse configurations verbosity = <4>; // 0: Disabled: 1: Critical, 2: Error, 3: Warn, 4: Info, 5: Debug uart_instance = <2>; emulate_prod_flow = <0>; // 1: emulate prod flow. For pre-prod only switch_bootchain = <0>; // 1: Switch to alternate Boot Chain on failure bootchain_switch_mechanism = <1>; // 1: use a/b boot reset_to_recovery = <1>; // 1: Switch to Forced Recovery on failure platform_detection_flow = <0>; //0: Boot in RCM flow for platform detection nv3p_checkSum = <1>; //1 Check-sum enabled for Nv3P command vrefRO_calib_override = <0>; //1: program VrefRO as per soft fuse VrefRO calibration value vrefRO_min_rev_tThreshold = <1>; vrefRO_calib_val = <0>; osc_threshold_low = <0x30E>; osc_threshold_high = <0x375>; pmc_threshold_low = <0x59E>; pmc_threshold_high = <0x64E>; bootchain_retry_count = <0>; //Specifies the max count to retry a particular boot chain, Max value is cpu { ////////// cpu variables //////////nafll_cfg3 = <0x38000000>; nafll_ctrl1 = <0x0000000C>; nafll_ctrl2 = <0x22250000>; adc_vmon.enable = <0x0>; min_adc_fuse_rev = <1>; ccplex_platform_features = <0x00000>; clock_mode { clock_burst_policy = <15>; max_avfs_mode = <0x2E>; }; lut_sw_freq_req { sw_override_ndiv = <3>; ndiv = <102>; vfgain = <2>; sw_override_vfgain = <3>; }; nafll_coeff { mdiv = <3>; pdiv = <0x1>; fll_frug_main = <0x9>; fll_frug_fast = <0xb>; }; nafll_cfg2 { fll_init = <0xd>; fll_ldmem = <0xc>; fll_switch_ldmem = <0xa>; }; pllx_base { divm = <2>; divn = <104>; divp = <2>; enable = <1>; bypass = <0>; }; }; wp { waypoint0 { rails_shorted = <1>; vsense0_cg0 = <1>; }; }; ////////// sw_carveout variables ////////// carveout { misc { size = <0x800000>; // 8MB alignment = <0x800000>; // 8MB }; os { size = <0x08000000>; //128MB pref_base = <0x80000000>; alignment = <0x200000>; }; cpub1 { alignment = <0x200000>; size = <0x04000000>; // 64MB }; rcm { size = <0x0>; alignment = <0>; }; mb2 { size = <0x01000000>; //16MB alignment = <0x01000000>; //16MB }; tzdram { size = <0x01000000>; //16MB alignment = <0x00100000>; //1MB }; ////////// mc carveout alignment ////////// vpr { alignment = <0x100000>; }; gsc@6 { alignment = <0x400000>; }; gsc@7 { alignment = <0x100000>; }; gsc@8 { alignment = <0x100000>; }; gsc@9 { alignment = <0x800000>; }; gsc@10 { alignment = <0x100000>; }; gsc@12 { alignment = <0x100000>; }; gsc@17 { alignment = <0x200000>; }; gsc@19 { alignment = <0x2000000>; }; gsc@24 { alignment = <0x200000>; }; gsc@27 { alignment = <0x200000>; }; gsc@28 { alignment = <0x200000>; }; gsc@29 { alignment = <0x200000>; }; }; ////////// mb1 ast va ////////// ast{ mb2_va = <0x52000000>; misc_carveout_va = <0x70000000>; rcm_blob_carveout_va = <0x60000000>; temp_map_a_carveout_va = <0x80000000>; temp_map_a_carveout_size = <0x40000000>; temp_map_b_carveout_va = <0xc0000000>; temp_map_b_carveout_size = <0x20000000>; }; ////////// clock variables ////////// clock { pllaon_divp = <0x3>; pllaon_divn = <0x1F>; pllaon_divm = <0x1>; pllaon_divn_frac = <0x03E84000>; // For bpmp_cpu_nic, bpmp_apb, axi_cbb and se, // specify the divider with PLLP_OUT0 (408MHz) as source. // For aon_cpu_nic, aon_can0 and aon_can1, // specify the divider with PLLAON_OUT as source. // In both cases, BCT specified value = (1 + expected divider value). bpmp_cpu_nic_divider = <1>; bpmp_apb_divider = <1>; axi_cbb_divider = <1>; se_divider = <1>; }; ////////// aotag variables ////////// aotag { boot_temp_threshold = <97000>; cooldown_temp_threshold = <87000>; cooldown_temp_timeout = <30000>; enable_shutdown = <1>; }; //////// aocluster data //////// aocluster { evp_reset_addr = <0xc480000>; }; }; }; Here is the old CFG format: .. code-block:: none disable_spe = 0; enable_vpr_resize = 0; disable_sc7 = 1; disable_fuse_visibility = 0; disable_mb2_glitch_protection = 0; carveout_alloc_direction = 2; ////////// cpu variables ////////// cpu.ccplex_platform_features = 0x00000; cpu.clock_mode.clock_burst_policy = 15; cpu.clock_mode.max_avfs_mode = 0x2E; cpu.lut_sw_freq_req.sw_override_ndiv = 3; cpu.lut_sw_freq_req.ndiv = 102; cpu.lut_sw_freq_req.vfgain = 2; cpu.lut_sw_freq_req.sw_override_vfgain = 3; cpu.nafll_coeff.mdiv = 3; cpu.nafll_coeff.pdiv = 0x1; cpu.nafll_coeff.fll_frug_main = 0x9; cpu.nafll_coeff.fll_frug_fast = 0xb; cpu.nafll_cfg2.fll_init = 0xd; cpu.nafll_cfg2.fll_ldmem = 0xc; cpu.nafll_cfg2.fll_switch_ldmem = 0xa; cpu.nafll_cfg3 = 0x38000000; cpu.nafll_ctrl1 = 0x0000000C; cpu.nafll_ctrl2 = 0x22250000; cpu.adc_vmon.enable = 0x0; cpu.pllx_base.divm = 2; cpu.pllx_base.divn = 104; cpu.pllx_base.divp = 2; cpu.pllx_base.enable = 1; cpu.pllx_base.bypass = 0; cpu.min_adc_fuse_rev = 1; wp.waypoint0.rails_shorted = 1; wp.waypoint0.vsense0_cg0 = 1; ////////// sw_carveout variables //////////carveout.misc.size = 0x800000; // 8MB carveout.misc.alignment = 0x800000; // 8MB carveout.os.size = 0x08000000; //128MB carveout.os.pref_base = 0x80000000; carveout.os.alignment = 0x200000; carveout.cpubl.alignment = 0x200000; firmware.cpubl_load_offset = 0x600000; carveout.cpubl.size = 0x04000000; // 64MB carveout.rcm.size = 0x0; carveout.rcm.alignment = 0; carveout.mb2.size = 0x01000000; //16MB carveout.mb2.alignment = 0x01000000; //16MB carveout.tzdram.size = 0x01000000; //16MB carveout.tzdram.alignment = 0x00100000; //1MB ////////// mc carveout alignment //////////carveout.vpr.alignment = 0x100000; carveout.gsc[6].alignment = 0x400000; carveout.gsc[7].alignment = 0x800000; carveout.gsc[8].alignment = 0x100000; carveout.gsc[9].alignment = 0x100000; carveout.gsc[10].alignment = 0x800000; carveout.gsc[12].alignment = 0x100000; carveout.gsc[17].alignment = 0x100000; carveout.gsc[19].alignment = 0x200000; carveout.gsc[24].alignment = 0x2000000; carveout.gsc[27].alignment = 0x200000; carveout.gsc[28].alignment = 0x200000; carveout.gsc[29].alignment = 0x200000; ////////// mb1 ast va ////////// ast.mb2_va = 0x52000000; ast.misc_carveout_va = 0x70000000; ast.rcm_blob_carveout_va = 0x60000000; ast.temp_map_a_carveout_va = 0x80000000; ast.temp_map_a_carveout_size = 0x40000000; ast.temp_map_b_carveout_va = 0xc0000000; ast.temp_map_b_carveout_size = 0x20000000; ////////// MB2 AST VA ////////// carveout.bpmp_ast_va = 0x50000000; carveout.ape_ast_va = 0x80000000; carveout.apr_ast_va = 0xC0000000; carveout.sce_ast_va = 0x70000000; carveout.rce_ast_va = 0x70000000; carveout.camera_task_ast_va = 0x78000000; ////////// clock variables ////////// clock.pllaon_divp = 0x3; clock.pllaon_divn = 0x1F; clock.pllaon_divm = 0x1; clock.pllaon_divn_frac = 0x03E84000; // For bpmp_cpu_nic, bpmp_apb, axi_cbb and se, // specify the divider with PLLP_OUT0 (408MHz) as source. // For aon_cpu_nic, aon_can0 and aon_can1, // specify the divider with PLLAON_OUT as source. // In both cases, BCT specified value = (1 + expected divider value). clock.bpmp_cpu_nic_divider = 1; clock.bpmp_apb_divider = 1; clock.axi_cbb_divider = 1; clock.se_divider = 1; ////////// aotag variables ////////// aotag.boot_temp_threshold = 97000; aotag.cooldown_temp_threshold = 87000; aotag.cooldown_temp_timeout = 30000; aotag.enable_shutdown = 1; //Specify i2c bus speed in KHz i2c.4 = 918; //////// aocluster data ////////aocluster.evp_reset_addr = 0xc480000; //////// mb2 feature flags //////// enable_sce = 1; enable_rce = 1; enable_ape = 1; enable_combined_uart = 1; spe_uart_instance = 2;