.. _SD.Bootloader.PinmuxGpioConfig:

.. include:: /content/swdocs.rsts

.. spelling::
   pad
   init
   DTS
   sdmmc
   hv
   eqos
   io
   ao
   ufs
   qspi
   DTSI
   SoC
   PMC
   IMPL
   bct
   GPIO
   pinmux
   dtsi
   pinctrl
   lpdr
   tristate
   ps
   PADCTL
   

Pinmux and GPIO Configuration
!!!!!!!!!!!!!!!!!!!!!!!!!!!!!

The pinmux configuration file provides pinmux and GPIO configuration, which is generated by using the pinmux spreadsheet. The stark contrast in the New DTS format with respect to the old legacy format is because of the pinmux sheet output. 

The pinmux DTS file is in the ``hardware/nvidia/platform/t23x/<platform>/bct/`` directory.

Here is the new DTS format example of a pad-voltage configuration file:

.. code-block:: none

   /*This dtsi file was generated by e3360_1099_slt_a01.xlsm Revision: 126 */
   
   #include <dt-bindings/pinctrl/pinctrl-tegra.h>
   
   / {
      pmc@2430000 {
         pinctrl-names = "default", "drive", "unused";
         pinctrl-0 = <&pinmux_default>;
         pinctrl-1 = <&drive_default>;
         pinctrl-2 = <&pinmux_unused_lowpower>;

         pinmux_default: common {
            nvidia,pins = "dap1_sclk_ps0";
            nvidia,function = "i2s1";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         dap1_dout_ps1 {
            nvidia,pins = "dap1_dout_ps1";
            nvidia,function = "i2s1";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         dap1_din_ps2 {
            nvidia,pins = "dap1_din_ps2";
            nvidia,function = "i2s1";
            nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         dap1_fs_ps3 {
            nvidia,pins = "dap1_fs_ps3";
            nvidia,function = "i2s1";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         aud_mclk_ps4 {
            nvidia,pins = "aud_mclk_ps4";
            nvidia,function = "aud";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         soc_gpio31_ps6 {
            nvidia,pins = "soc_gpio31_ps6";
            nvidia,function = "sdmmc1";
            nvidia,pull = <TEGRA_PIN_PULL_UP>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         soc_gpio32_ps7 {
            nvidia,pins = "soc_gpio32_ps7";
            nvidia,function = "spdif";
            nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
            nvidia,tristate = <TEGRA_PIN_ENABLE>;
            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };

         soc_gpio33_pt0 {
            nvidia,pins = "soc_gpio33_pt0";
            nvidia,function = "spdif";
            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
            nvidia,tristate = <TEGRA_PIN_DISABLE>;
            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
         };
      };

      drive_default: drive {
      };
   };
 };

.. note::
   In the kernel, some Pinmux configurations in MB1 BCT might be overridden.
   
   In the SPI2_MOSI pin, for example, to remove the following node from the kernel device tree:
.. code-block:: none

   dsi_vdd_1v8_bl_en: regulator@116 {
      compatible = "regulator-fixed";
      reg = <116>;
      regulator-name = "dsi-vdd-1v8-bl-en";
      regulator-min-microvolt = <1800000>;
      regulator-max-microvolt = <1800000>;
      vin-supply = <&p3737_vdd_1v8_sys>;
      gpio = <&tegra_aon_gpio TEGRA234_AON_GPIO(CC, 2) 0>; //CAM_INT3, GPIO_ACTIVE_HIGH == 0
      enable-active-high;
   };

Here is the previous CFG format:


.. code-block:: none

   //////// Pinmux for used pins ////////
   pinmux.0x02434060 = <value1>; // gen1_i2c_scl_pc5.PADCTL_CONN_GEN1_I2C_SCL_0 
   pinmux.0x02434064 = <value2>; // gen1_i2c_scl_pc5.PADCTL_CONN_CFG2TMC_GEN1_I2C_SCL_0 
   pinmux.0x02434068 = <value1>; // gen1_i2c_sda_pc6.PADCTL_CONN_GEN1_I2C_SDA_0 
   pinmux.0x0243406C = <value2>; // gen1_i2c_sda_pc6.PADCTL_CONN_CFG2TMC_GEN1_I2C_DA_0
   
   //////// Pinmux for unused pins for low-power configuration ////////
   pinmux.0x02434040 = <value1>; // gpio_wan4_ph0.PADCTL_CONN_GPIO_WAN4_0
   pinmux.0x02434044 = <value2>; // gpio_wan4_ph0.PADCTL_CONN_CFG2TMC_GPIO_WAN4_0 
   pinmux.0x02434048 = <value1>; // gpio_wan3_ph1.PADCTL_CONN_GPIO_WAN3_0
   pinmux.0x0243404C = <value2>; // gpio_wan3_ph1.PADCTL_CONN_CFG2TMC_GPIO_WAN3_0