Jetson Sensor Processing Engine (SPE) Developer Guide

r35.6 Release
SPI application (app/spi-app.c)

Table of Contents

SPI application demonstrates how to access/manipulate Always On (AON) SPI from the SPE/AON processor. SPI 2 is in AON domain for both Jetson AGX Xavier and Orin. The The app uses loop back test. It sends predefined bytes and compares sent bytes with received, on success it should print "SPI test successful".

Note
It is required to compile device tree and flash board to have device tree updated after making kernel device tree changes as described in following sections.

Jetson AGX Xavier

Hardware Configuration

User must short MISO and MOSI signals (follow below sections for pin map) in order to successfully run this app. SPI 2 signals are available at connector J6 with below pin mappings.

  • Pin A5 - CLK
  • Pin A6 - MISO
  • Pin A7 - MOSI
  • Pin A8 - CS0

Software Configuration

  1. Disable SPI driver in the Linux kernel device tree and ensure that no other processors using the driver. Run source_sync.sh and the resulting dtsi file is located at Linux_for_Tegra/sources/hardware/nvidia/platform/t19x/common/kernel-dts/t19x-common-modules/tegra194-camera-e3377-a00.dtsi
spi@c260000 {
status = "disabled";
spi-max-frequency = <12000000>;
...
}
  1. In soc/t19x/target_specific.mk, set ENABLE_SPI_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t194.bin
  2. Reflash all the paritions including new device tree and SPE binaries generated from the above steps.

Jetson AGX Orin

Hardware Configuration

User must short MISO and MOSI signals (follow below sections for pin map) in order to successfully run this app. SPI 2 signals are available at connector J3 with below pin mappings.

  • Pin E61 - CLK
  • Pin D62 - MISO
  • Pin F60 - MOSI
  • Pin D60 - CS0

Software Configuration

  1. Pinmuxing updates are recommended via generating new dtsi files using the pinmux spreadsheet. For the purpose of performing a quick test, the pinmux files can be manually updated by editing ${L4T}/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi: 
            --- a/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
        +++ b/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
        @@ -915,18 +915,18 @@

                                spi2_sck_pcc0 {
                                        nvidia,pins = "spi2_sck_pcc0";
        -                               nvidia,function = "rsvd1";
        -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
        -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
        -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        +                               nvidia,function = "spi2";
        +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
        +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
        +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                        nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                                };

                                spi2_miso_pcc1 {
                                        nvidia,pins = "spi2_miso_pcc1";
        -                               nvidia,function = "rsvd1";
        -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
        +                               nvidia,function = "spi2";
        +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
        @@ -935,20 +935,20 @@

                                spi2_mosi_pcc2 {
                                        nvidia,pins = "spi2_mosi_pcc2";
        -                               nvidia,function = "rsvd1";
        -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
        -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
        -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        +                               nvidia,function = "spi2";
        +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
        +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
        +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                        nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                                };

                                spi2_cs0_pcc3 {
                                        nvidia,pins = "spi2_cs0_pcc3";
        -                               nvidia,function = "rsvd1";
        -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
        -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
        -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
        +                               nvidia,function = "spi2";
        +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
        +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
        +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                        nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                                };
  2. Update gpio configuration as below in ${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi: 
         --- a/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
     +++ b/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
     @@ -125,10 +125,6 @@
                                     TEGRA234_AON_GPIO(EE, 6)
                                     TEGRA234_AON_GPIO(EE, 2)
                                     TEGRA234_AON_GPIO(EE, 4)
     -                               TEGRA234_AON_GPIO(CC, 0)
     -                               TEGRA234_AON_GPIO(CC, 1)
     -                               TEGRA234_AON_GPIO(CC, 2)
     -                               TEGRA234_AON_GPIO(CC, 3)
                                     TEGRA234_AON_GPIO(AA, 0)
  3. Modify firewall setting in ${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts to allow SPE to read/write to the SPI2 register. 
         +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
     @@ -24,6 +24,11 @@
                    value = <0x18000606>;
                };

     +          reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
     +              exclusion-info = <3>;
     +              value = <0x30001410>;
     +          };
     +
                reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
  4. In soc/t23x/target_specific.mk, set ENABLE_SPI_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t234.bin.
  5. Reflash all partitions to ensure that the pinmux and firewall settings are updated on the board.

Jetson Orin Nano

Hardware Configuration

User must short MISO and MOSI signals (follow below sections for pin map) in order to successfully run this app. SPI 2 signals are available at connector J2 with below pin mappings.

  • Pin 126 - CLK
  • Pin 127 - MISO
  • Pin 128 - MOSI
  • Pin 130 - CS0

Software Configuration

  1. Pinmuxing updates are recommended via generating new dtsi files using the pinmux spreadsheet. For the purpose of performing a quick test, the pinmux files can be manually updated by editing ${L4T}/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi: 
            --- a/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
        +++ b/bootloader/t186ref/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
        @@ -608,7 +608,7 @@

                                spi2_sck_pcc0 {
                                        nvidia,pins = "spi2_sck_pcc0";
        -                               nvidia,function = "rsvd1";
        +                               nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        @@ -618,17 +618,17 @@

                                spi2_miso_pcc1 {
                                        nvidia,pins = "spi2_miso_pcc1";
        -                               nvidia,function = "rsvd1";
        +                               nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
        -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
        -                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
        +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
        +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                        nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
                                        nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                                };

                                spi2_mosi_pcc2 {
                                        nvidia,pins = "spi2_mosi_pcc2";
       -                                nvidia,function = "rsvd1";
       +                                nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;
       @@ -638,7 +638,7 @@

                               spi2_cs0_pcc3 {
                                        nvidia,pins = "spi2_cs0_pcc3";
       -                                nvidia,function = "rsvd1";
       +                                nvidia,function = "spi2";
                                        nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                        nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                        nvidia,enable-input = <TEGRA_PIN_DISABLE>;
  2. Update gpio configuration as below in ${L4T}/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi: 
       --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
   +++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
   @@ -91,13 +91,9 @@
                                   TEGRA234_AON_GPIO(EE, 4)
                                   >;
                           gpio-output-low = <
   -                               TEGRA234_AON_GPIO(CC, 0)
   -                               TEGRA234_AON_GPIO(CC, 2)
   -                               TEGRA234_AON_GPIO(CC, 3)
                                   TEGRA234_AON_GPIO(AA, 4)
                                   >;
                           gpio-output-high = <
   -                               TEGRA234_AON_GPIO(CC, 1)
                                   TEGRA234_AON_GPIO(AA, 5)
                                   TEGRA234_AON_GPIO(BB, 3)
                                   >;
  3. Modify firewall setting in ${L4T}/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts to allow SPE to read/write to the SPI2 register. 
         +++ b/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts
     @@ -810,6 +810,10 @@
                           exclusion-info = <0>;
                           value = <0x00000000>;
                           };
     +                     reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
     +                     exclusion-info = <3>;
     +                     value = <0x30001410>;
     +                     };
                           reg@2228 { /* CLK_RST_CONTROLLER_ERR_COLLATOR_FSI_SCR_EC_SCR_0 */
                           exclusion-info = <0>;
  4. In soc/t23x/target_specific.mk, set ENABLE_SPI_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t234.bin.
  5. Reflash all partitions to ensure that the pinmux and firewall settings are updated on the board.

Result

The demo app sends predefined data. Test is successful if app retrieves the same data and should print "SPI test successful".