Jetson Sensor Processing Engine (SPE) Developer Guide

r36.3 Release
GPIO Application (app/gpio-app.c)

Table of Contents

GPIO application demonstrates how to access/manipulate Always On (AON) GPIOs from the SPE/AON processor.

Pinmux changes are necessary in order for this demo to function correctly. These changes relate to the MB1 bootloader. The recommended method for changing pinmux settings is to download the device-specific pinmux spreadsheet and generate an updated set of pinmux configuration files. In the steps below some updates to various configuration files will be shown. While the preferred method is to leverage the pinmux spreadsheet, manually modifying the files will also work for the purpose of quickly demonstrating GPIO functionality.

AGX Orin

Hardware Configuration

The following pins from the 40 pin header (J30) should be connected together:

  • Pin 16 (PBB1, output)
  • Pin 32 (PBB0, input)

Software Configuration

In order to access a AON GPIO from the Cortex-R5 SPE/AON for AGX Orin, the GPIO interrupt map and pinmux settings need to be updated as described in below steps.

  1. In soc/t23x/target_specific.mk, set ENABLE_GPIO_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t234.bin.
  2. Update gpio interrupt mapping as below in ${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts: 
      --- a/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts
  +++ b/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts
  @@ -234,7 +234,7 @@
              pin-7-int-line = <4>; // GPIO AA7 to INT0
           };
           port@BB {
  -            pin-0-int-line = <4>; // GPIO BB0 to INT0
  +            pin-0-int-line = <2>; // GPIO BB0 to INT2
              pin-1-int-line = <4>; // GPIO BB1 to INT0
              pin-2-int-line = <4>; // GPIO BB2 to INT0
              pin-3-int-line = <4>; // GPIO BB3 to INT0
  3. Update gpio configuration as below in ${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi: 
      --- a/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
  +++ b/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
  @@ -118,12 +118,12 @@
                                TEGRA234_AON_GPIO(AA, 2)
                                TEGRA234_AON_GPIO(AA, 3)
                                TEGRA234_AON_GPIO(BB, 0)
  -                              TEGRA234_AON_GPIO(BB, 1)
                                TEGRA234_AON_GPIO(BB, 3)
                                >;
                          gpio-output-low = <
                                TEGRA234_AON_GPIO(CC, 2)
                                TEGRA234_AON_GPIO(CC, 3)
  +                              TEGRA234_AON_GPIO(BB, 1)
                                >;
                          gpio-output-high = <
                                >;
  4. Update pinmux configuration as below in the file ${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi: 
      --- a/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
  +++ b/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
  @@ -1000,9 +1000,9 @@
                          can1_en_pbb1 {
                                nvidia,pins = "can1_en_pbb1";
                                nvidia,function = "rsvd0";
  -                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
  -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
  -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
  +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
  +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
  +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                          };
  5. Reflash all partitions to ensure that the gpio interrupt mappings and pinmux settings are updated on the board.
  6. The demo should produce the following output on the terminal: 
      gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
  can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0

Orin Nano

Hardware Configuration

The following pins from the 40 pin header (J12) should be connected together:

  • Pin 5 (PDD1, output)
  • Pin 3 (PDD2, input)

Software Configuration

In order to access a AON GPIO from the Cortex-R5 SPE/AON for Orin Nano, the GPIO interrupt map and pinmux settings need to be updated as described in below steps.

  1. In soc/t23x/target_specific.mk, set ENABLE_GPIO_APP := 1 and ENABLE_SPE_FOR_ORIN_NANO := 1. Rebuild the application. Copy the output to${L4T}/bootloader/spe_t234.bin`.
  2. Update gpio interrupt mapping as below in ${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts: 
      --- a/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts
  +++ b/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts
  @@ -252,7 +252,7 @@
           port@DD {
              pin-0-int-line = <4>; // GPIO DD0 to INT0
              pin-1-int-line = <4>; // GPIO DD1 to INT0
  -           pin-2-int-line = <4>; // GPIO DD2 to INT0
  +           pin-2-int-line = <2>; // GPIO DD2 to INT2
           };
  3. Update gpio configuration as below in ${L4T}/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi: 
      --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
  +++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
  @@ -89,8 +89,10 @@
                          gpio-input = <
                                TEGRA234_AON_GPIO(EE, 2)
                                TEGRA234_AON_GPIO(EE, 4)
  +                             TEGRA234_AON_GPIO(DD, 2)
                                >;
                          gpio-output-low = <
  +                             TEGRA234_AON_GPIO(DD, 1)
                                TEGRA234_AON_GPIO(CC, 0)
  4. Update pinmux configuration as below in the file ${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi:
     --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
     +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
     @@ -134,19 +134,18 @@

                             gen8_i2c_scl_pdd1 {
                                     nvidia,pins = "gen8_i2c_scl_pdd1";
     -                               nvidia,function = "i2c8";
     +                               nvidia,function = "rsvd1";
                                     nvidia,pull = <TEGRA_PIN_PULL_NONE>;
                                     nvidia,tristate = <TEGRA_PIN_DISABLE>;
     -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
     +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                                     nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                     nvidia,lpdr = <TEGRA_PIN_DISABLE>;
                             };

                             gen8_i2c_sda_pdd2 {
                                     nvidia,pins = "gen8_i2c_sda_pdd2";
     -                               nvidia,function = "i2c8";
     -                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
     -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
     +                               nvidia,function = "rsvd1";
     +                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
     +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
                                     nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                                     nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
                                     nvidia,lpdr = <TEGRA_PIN_DISABLE>;
  1. Reflash all partitions to ensure that the gpio interrupt mappings and pinmux settings are updated on the board.
  2. The demo should produce the following output on the terminal: 
      gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
  can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0