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Jetson Sensor Processing Engine (SPE) Developer Guider36.3 Release |
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Jetson Sensor Processing Engine (SPE) Developer Guider36.3 Release |
SPI application demonstrates how to access/manipulate Always On (AON) SPI from the SPE/AON processor. SPI 2 is in AON domain for both Jetson AGX Orin and Orin Nano. The The app uses loop back test. It sends predefined bytes and compares sent bytes with received, on success it should print "SPI test successful".
User must short MISO and MOSI signals (follow below sections for pin map) in order to successfully run this app. SPI 2 signals are available at connector J3 with below pin mappings.
${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi: --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
@@ -915,18 +915,18 @@
spi2_sck_pcc0 {
nvidia,pins = "spi2_sck_pcc0";
- nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi2_miso_pcc1 {
nvidia,pins = "spi2_miso_pcc1";
- nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
@@ -935,20 +935,20 @@
spi2_mosi_pcc2 {
nvidia,pins = "spi2_mosi_pcc2";
- nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi2_cs0_pcc3 {
nvidia,pins = "spi2_cs0_pcc3";
- nvidia,function = "rsvd1";
- nvidia,pull = <TEGRA_PIN_PULL_UP>;
- nvidia,tristate = <TEGRA_PIN_ENABLE>;
- nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi: --- a/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+++ b/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
@@ -125,10 +125,6 @@
TEGRA234_AON_GPIO(EE, 6)
TEGRA234_AON_GPIO(EE, 2)
TEGRA234_AON_GPIO(EE, 4)
- TEGRA234_AON_GPIO(CC, 0)
- TEGRA234_AON_GPIO(CC, 1)
- TEGRA234_AON_GPIO(CC, 2)
- TEGRA234_AON_GPIO(CC, 3)
TEGRA234_AON_GPIO(AA, 0)
${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts to allow SPE to read/write to the SPI2 register. +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
@@ -24,6 +24,11 @@
value = <0x18000606>;
};
+ reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
+ exclusion-info = <3>;
+ value = <0x30001410>;
+ };
+
reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
soc/t23x/target_specific.mk, set ENABLE_SPI_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t234.bin.User must short MISO and MOSI signals (follow below sections for pin map) in order to successfully run this app. SPI 2 signals are available at connector J2 with below pin mappings.
${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi: --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
@@ -608,7 +608,7 @@
spi2_sck_pcc0 {
nvidia,pins = "spi2_sck_pcc0";
- nvidia,function = "rsvd1";
+ nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -618,17 +618,17 @@
spi2_miso_pcc1 {
nvidia,pins = "spi2_miso_pcc1";
- nvidia,function = "rsvd1";
+ nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
- nvidia,tristate = <TEGRA_PIN_DISABLE>;
- nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
nvidia,lpdr = <TEGRA_PIN_DISABLE>;
};
spi2_mosi_pcc2 {
nvidia,pins = "spi2_mosi_pcc2";
- nvidia,function = "rsvd1";
+ nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
@@ -638,7 +638,7 @@
spi2_cs0_pcc3 {
nvidia,pins = "spi2_cs0_pcc3";
- nvidia,function = "rsvd1";
+ nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
${L4T}/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi: --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
@@ -91,13 +91,9 @@
TEGRA234_AON_GPIO(EE, 4)
>;
gpio-output-low = <
- TEGRA234_AON_GPIO(CC, 0)
- TEGRA234_AON_GPIO(CC, 2)
- TEGRA234_AON_GPIO(CC, 3)
TEGRA234_AON_GPIO(AA, 4)
>;
gpio-output-high = <
- TEGRA234_AON_GPIO(CC, 1)
TEGRA234_AON_GPIO(AA, 5)
TEGRA234_AON_GPIO(BB, 3)
>;
${L4T}/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts to allow SPE to read/write to the SPI2 register. +++ b/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts
@@ -810,6 +810,10 @@
exclusion-info = <0>;
value = <0x00000000>;
};
+ reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
+ exclusion-info = <3>;
+ value = <0x30001410>;
+ };
reg@2228 { /* CLK_RST_CONTROLLER_ERR_COLLATOR_FSI_SCR_EC_SCR_0 */
exclusion-info = <0>;
soc/t23x/target_specific.mk, set ENABLE_SPI_APP := 1 and rebuild the application. Copy the output to ${L4T}/bootloader/spe_t234.bin.The demo app sends predefined data. Test is successful if app retrieves the same data and should print "SPI test successful".