Jetson Sensor Processing Engine (SPE) Developer Guide

r36.4 Release

GTE Application (app/gte-app.c)

This section explains how to use the generic time-stamping engine (GTE).

The GTE snoops a set of signals and presents the timestamped events to the software using FIFOs. There are three GTE instances/slices available to AON/SPE and each is 32 bits wide. Refer to gte-tegra-hw.h for more information about signals mapping to slices.

To determine the GTE pin mapping, refer to the pin-mux spreadsheet that corresponds to your module. There is a hidden column in the spreadsheet called "GTE" that lists the bit in slice 2 that corresponds to that pin.

Hardware Configuration

The application demonstrates the GTE driver APIs and works with gpio-app to monitor the interrupt on the GPIO_APP_IN line. Refer to GPIO Application, for more information about wiring details.

Software Configuration

AGX Orin

  1. In soc/t23x/target_specific.mk, set ENABLE_GTE_APP := 1, rebuild the application, and copy the output to ${L4T}/bootloader/spe_t234.bin.
  2. Disable GTE driver in the Linux kernel device tree, ensure that no other processors using the driver, and run source_sync.sh. The resulting dtsi file is located at Linux_for_Tegra/sources/hardware/nvidia/t23x/nv-public/overlay/tegra234-p3737-0000+p3701-0000.dts. Add the following code to disable hardware-timestamp under bus0 node.
         +++ tegra234-p3737-0000+p3701-0000.dts
         @@ -210,6 +210,10 @@
                                        status = "okay";
                                };
    
         +                hardware-timestamp@c1e0000 {
         +                       status = "disabled";
         +                };
         +
                          mttcan@c310000 {
                                 status = "okay";
    
  3. Rebuild the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
  4. Modify firewall setting in ${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts to allow SPE to read/write to the GTE register.
    +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
    @@ -24,6 +24,11 @@
    value = <0x18000606>;
    };
    + reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
    + exclusion-info = <2>;
    + value = <0x38001232>;
    + };
    +
    reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
  5. Reflash all partitions to ensure that the dtb and firewall settings are updated on the board.

Orin Nano

  1. In soc/t23x/target_specific.mk, set ENABLE_GTE_APP := 1 and ENABLE_SPE_FOR_ORIN_NANO := 1. Rebuild the application, and copy the output to ${L4T}/bootloader/spe_t234.bin.
  2. Disable GTE driver in the Linux kernel device tree, ensure that no other processors using the driver, and run source_sync.sh. The resulting dtsi file is located at Linux_for_Tegra/sources/hardware/nvidia/t23x/nv-public/overlay/tegra234-p3768-0000+p3767-0000.dts. Add the following code to disable hardware-timestamp under bus0 node.
         +++ tegra234-p3768-0000+p3767-0000.dts
         @@ -245,6 +245,10 @@
                                        status = "okay";
                                };
    
         +                hardware-timestamp@c1e0000 {
         +                       status = "disabled";
         +                };
         +
                          mttcan@c310000 {
                                 status = "okay";
    
  3. Rebuild the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
  4. Modify firewall setting in ${L4T}/bootloader/tegra234-firewall-config-base.dtsi to allow SPE to read/write to the GTE register.
    +++ b/bootloader/tegra234-firewall-config-base.dtsi
    @@ -6814,7 +6814,7 @@
    };
    reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
    exclusion-info = <3>;
    - value = <0x38000222>;
    + value = <0x38001232>;
    };
  5. Reflash all partitions to ensure that the dtb and firewall settings are updated on the board.

Result

GTE ISR is called when the FIFO reaches the GTE_FIFO_OCCUPANCY threshold. On successful execution, GTE ISR following message:

gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
Slice Id: xx, Event Id: xx (Other), Edge = rising, Raw Time stamp = xx, Timestamp in nanosec = xx
can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0