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Jetson Sensor Processing Engine (SPE) Developer Guider32.6.1 Release |
This section explains how to use the CAN application on NVIDIA® Jetson™ NVIDIA Jetson TX2, Jetson AGX Xavier, and Jetson Xavier NX.
There are two CAN controllers, which run in Always On (AON) mode. The application demonstrates how to use CAN controller driver APIs.
To control compilation of the CAN application, use the ENABLE_CAN_APP
, ENABLE_CAN_TX
and ENABLE_CAN_RX
flags in the soc/*/target_specific.mk
file. Follow the platform-specific sections below to use the ENABLE_CAN_TX and ENABLE_CAN_RX
flags.
Before you can successfully execute the application, you must obtain two CAN transceivers. The transceivers must be 3.3V I/O compatible, similar to the ones at:
https://www.amazon.com/SN65HVD230-CAN-Board-Communication-Development/dp/B00KM6XMXO
By default, the CAN AON controller driver sets the bit rate to 500 Kb/second and the data bit rate to 2 Mb/second. For more information, see the mttcan_controller_init
function in the tegra-can.c
driver source file.
The application prints the details below upon successful CAN message transmission, and prints the transmitted element, which includes information about the transmitted message. The transmit element is also created when there is a bus state change.
Transmited message from CAN <controller number> Transmission complete event Transmit event element information: Message ID: 0xa5, Event Type: Tx event, CAN Frame: <frame details>
The application prints the details below upon successful CAN message reception.
Message received at CAN <controller number> Message ID: 0xa5, Message data length: 2 Message Data: 0xaa 0x55
The application uses both AON CAN controllers, so you must set both the flags ENABLE_CAN_TX and ENABLE_CAN_RX
to 1. Additionally, define ENABLE_CAN0_AS_TX
and ENABLE_CAN1_AS_RX
macros in can-app.c
. This connects the CAN0 bus to CAN1 using the CAN transceivers and the diagram above, where:
Ensure that the CAN is disabled in the kernel device tree tegra186-quill-p3310-1000-c03-00-base.dts
as shown below:
CAN 0 and 1 controller TX and RX are brought out to 30 pin header J26 as below:
Additional 3.3V and GND connections are available at 40 pin header J21 as below:
The application uses both AON CAN controllers, so you must set both the flags ENABLE_CAN_TX and ENABLE_CAN_RX
to 1. Additionally, define ENABLE_CAN0_AS_TX
and ENABLE_CAN1_AS_RX
macros in can-app.c
. This connects the CAN0 bus to CAN1 using the CAN transceivers and the diagram above, where:
Ensure that the CAN is disabled in the kernel device tree tegra194-p2888-0001-p2822-0000-common.dtsi
as shown below:
Modify the SCR setting in tegra194-mb1-bct-scr-cbb-mini.cfg
as follows:
Modify the pinmux setting in tegra19x-mb1-pinmux-p2888-0000-a04-p2822-0000-b01.cfg
as follows:
CAN 0 and 1 controller TX and RX are brought out to 40 pin header J30 as below:
The application uses only AON CAN 0 controller, that is the only controller exposed to the user. Conceptually it follows the same diagram as mentioned above , where one end will be configured as CAN TX and other as CAN RX. The following test setup steps assume that two Jetson NX platforms are used to run the application.
On Jetson NX acting as CAN transmitter:
ENABLE_CAN_TX
to 1 and ENABLE_CAN_RX
to 0.ENABLE_CAN0_AS_TX
macro in can-app.c
file.On Jetson NX acting as CAN receiver:
ENABLE_CAN_TX
to 0 and ENABLE_CAN_RX
to 1.ENABLE_CAN0_AS_RX
macro in can-app.c
file.This connects the CAN0 bus of one Jetson NX to CAN0 of another Jetson NX, using the above mentioned CAN transceivers and diagram, where:
Ensure that the CAN is disabled in the kernel device tree tegra194-p3668-common.dtsi
as shown below:
Modify the SCR setting in tegra194-mb1-bct-scr-cbb-mini-p3668.cfg
as follows:
Modify the pinmux setting in tegra19x-mb1-pinmux-p3668-a01.cfg
as follows:
CAN 0 is brought out to 4 pin header J17 as below: