cupva_host_common.hpp

Fully qualified name: src/host/shared/include/install/cupva_host_common.hpp

File members: src/host/shared/include/install/cupva_host_common.hpp

/*
 * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
 *
 * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
 * property and proprietary rights in and to this material, related
 * documentation and any modifications thereto. Any use, reproduction,
 * disclosure or distribution of this material and related documentation
 * without an express license agreement from NVIDIA CORPORATION or
 * its affiliates is strictly prohibited.
 */

#ifndef CUPVA_HOST_COMMON_HPP
#define CUPVA_HOST_COMMON_HPP

#include <array>
#include <cstddef>
#include <cstdint>
#include <stdexcept>

static_assert(CUPVA_DEVICE == 0, "cupva_host_common.hpp should not be used in device code");

#ifndef DLL_EXPORT
#    define DLL_EXPORT __attribute__((visibility("default")))
#endif

namespace cupva {

namespace config {
constexpr int32_t MAX_L2SRAM_SIZE{1048576}; //2 * 512 * 1024

constexpr int32_t MAX_SYMBOL_LENGTH{64};

constexpr int32_t MAX_CMD_REQUEST_FENCES_ARRAY_SIZE{4};

constexpr int32_t MAX_CMD_WAIT_ON_FENCES_ARRAY_SIZE{8};

constexpr int32_t MAX_NUM_COMMANDS_PER_SUBMIT{256};

constexpr uint32_t ENGINE_MASK_ALL{UINT32_MAX};

constexpr uint32_t MAX_TOTAL_PARAM_SIZE{8192U};

constexpr uint32_t MAX_VPU_PRINT_BUFFER_SIZE{16777216U};
} // namespace config

enum OrderType : uint32_t
{
    IN_ORDER,
    OUT_OF_ORDER
};

enum class MemType : uint32_t
{
    DRAM,
    SRAM,
    VMEM
};

enum class SyncClientType : uint32_t
{
    SIGNALER,
    WAITER,
    SIGNALER_WAITER,
};

enum class SyncWaitMode : uint32_t
{
    YIELD,
    SPIN
};

enum SurfaceFormatType : uint32_t
{
    PITCH_LINEAR = 0,
    BLOCK_LINEAR
};

enum EngineType : uint32_t
{
    PVA0 = 0,
    PVA1 = 1
};

enum AffinityType : uint32_t
{
    VPU0 = 1,
    VPU1 = 2,
    VPU_ANY = 3,
};

enum PadModeType : uint32_t
{
    PAD_CONST = 0,
    PAD_BPE
};

enum PvaGeneration : uint32_t
{
    PVA_GEN_INVALID = 0,
    PVA_GEN1,
    PVA_GEN2,
    PVA_GEN3,
    PVA_GEN_MAX
};

enum ScanOrderType : uint32_t
{
    HORIZONTAL_REVERSED = (1U << 0U),
    VERTICAL_REVERSED = (1U << 1U),
    COLUMN_MAJOR = (1U << 2U),
    SCANORDER_MASK_ALL = (HORIZONTAL_REVERSED | VERTICAL_REVERSED | COLUMN_MAJOR),
};

struct HardwareInfo
{
    uint32_t pvaEngineCount;

    uint32_t pvaVPUCount;

    PvaGeneration pvaGen;
};

enum PadDirType : uint32_t
{
    PAD_NONE = 0,
    PAD_TOP = 1,
    PAD_BOTTOM = 2,
    INVALID_PAD_TOP_BOTTOM = 3,
    PAD_LEFT = 4,
    PAD_TOP_LEFT = 5,
    PAD_BOTTOM_LEFT = 6,
    INVALID_PAD_TOP_BOTTOM_LEFT = 7,
    PAD_RIGHT = 8,
    PAD_TOP_RIGHT = 9,
    PAD_BOTTOM_RIGHT = 10,
    INVALID_PAD = 11,
};

inline PadDirType operator|(PadDirType const a, PadDirType const b) noexcept
{
    uint32_t const retVal{static_cast<uint32_t>(a) | static_cast<uint32_t>(b)};
    if (retVal > static_cast<uint32_t>(INVALID_PAD))
    {
        return INVALID_PAD;
    }
    return static_cast<PadDirType>(retVal);
};

using char_t = char;

enum class GranType : uint32_t
{
    //transfers a tile
    TILE = 0,
    //transfers all tiles in 1st dimension
    DIM1,
    //transfers all tiles in 1st and 2nd dimensions
    DIM2,
    //transfers all tiles in the dataflow
    ALL
};

enum class TransferModeType : uint32_t
{
    TILE = 0,
    DIM1,
    DIM2,
    TRANSFER,
    CONTINUOUS
};

enum class Error : uint32_t
{
    None = 0,
    UnsupportedFeature,
    InternalError,
    InvalidState,
    InvalidArgument,
    UninitializedObject,
    DriverAPIError,
    CommandExecutionTimeout,
    CommandSubmissionTimeout,
    EngineInBadState,
    FenceStatusBufferFailure,
    VpuApplicationError,
    VpuDivideByZero,
    VpuFloatingPointNotANumber,
    VpuIllegalInstruction,
    VpuHalted,
    VpuDebugNotAllowed,
    VpuAborted,
    OperationPending,
    IncompatibleVersion,
    CUDADisabled,
    InsufficientDriverVersion,
    DlutError,
    DmaValidationFailed,
    ParameterValidationFailed,
    UnknownError,
    // NVIDIA DRIVE OS error code range starts
    PFSDChecksumMismatch,
    PFSDTimeout,
    NotAllowedInOperationalState,
    AbortedCmdBuffer,
    ErrorCodeMaxValue,
};

class DLL_EXPORT Exception : public std::exception
{
public:
    Exception(Error const errorCode, char_t const *const errorMsg) noexcept;

    ~Exception() noexcept override;

    Exception(Exception const &) noexcept;

    Exception &operator=(Exception const &) & noexcept;

    Exception(Exception &&) noexcept;

    Exception &operator=(Exception &&) & noexcept;

    Error getErrorCode() const noexcept;

    char_t const *what() const noexcept override;

    static constexpr uint32_t MAX_ERROR_MSG_LENGTH{768U};

private:
    Error m_errorCode;
    std::array<char_t, MAX_ERROR_MSG_LENGTH> m_errorMsg;
};

DLL_EXPORT const HardwareInfo &GetHardwareInfo();

DLL_EXPORT const uint32_t GetDriverVersion();

DLL_EXPORT const uint32_t GetRuntimeVersion() noexcept;

namespace impl {
// forward declaration of CmdStatus
struct CmdStatus;
} // namespace impl

using CmdStatus = impl::CmdStatus *;

DLL_EXPORT Error CheckCommandStatus(CmdStatus const status);

template<typename T, size_t SIZE, size_t ALIGN = alignof(std::max_align_t)>
class StaticStorage
{
    //StorageType is properly aligned uninitialized storage of size SIZE
    using StorageType = std::aligned_storage_t<SIZE, ALIGN>;

public:
    // ImplType is a typedef for the template type T
    using ImplType = T;

    StaticStorage() noexcept
        : m_data{}
    {
    }

    StaticStorage(const StaticStorage &obj) noexcept
        : StaticStorage()
    {
        *this = obj;
    }

    StaticStorage &operator=(const StaticStorage &obj) & noexcept = default;

    StaticStorage(StaticStorage &&obj) noexcept
        : StaticStorage{}
    {
        *this = std::move(obj);
    }

    auto operator=(StaticStorage &&obj) & noexcept -> StaticStorage &
    {
        using std::swap;
        swap(m_data, obj.m_data);
        return *this;
    }

    ~StaticStorage() = default;

    template<typename U = T>
    auto getImpl() noexcept -> U *
    {
        static_assert(std::is_base_of<T, U>::value, "invalid type cast!");
        static_assert(SIZE >= sizeof(U) && ALIGN % std::alignment_of<U>::value == 0,
                      "static storage size/alignment mismatch!");
        return static_cast<U *>(static_cast<void *>(&m_data));
    }

    template<typename U = T>
    auto getImpl() const noexcept -> const U *
    {
        static_assert(std::is_base_of<T, U>::value, "invalid type cast!");
        static_assert(SIZE >= sizeof(U) && ALIGN % std::alignment_of<U>::value == 0,
                      "static storage size/alignment mismatch!");
        return static_cast<const U *>(static_cast<const void *>(&m_data));
    }

private:
    // member data for class StaticStorage
    StorageType m_data;
};
namespace mem {

static constexpr int32_t SURFACE_ATTRIBUTES_MAX_NUM_PLANES{6};

enum class AllocType : uint32_t
{
    ALLOC_DRAM,
    ALLOC_CVSRAM
};

enum class BufferType : uint32_t
{
    SURFACE,
    RAW
};

enum class AccessType : uint32_t
{
    READ,
    WRITE,
    READ_WRITE
};

enum class L2SRAMPolicyType : uint32_t
{
    FILL = 1,

    FLUSH = 2,

    FILL_AND_FLUSH = 3
};

enum class L2OperationType : uint32_t
{
    FLUSH,

    INVALIDATE,

    FLUSH_AND_INVALIDATE
};

struct PlaneInfo
{
    int64_t offset;
    int32_t linePitch;
    int32_t widthInBytes;
    int32_t height;
};

struct SurfaceAttributes
{
    SurfaceFormatType format;
    int32_t numPlanes;
    std::array<PlaneInfo, SURFACE_ATTRIBUTES_MAX_NUM_PLANES> planes;
};

struct PointerAttributes
{
    BufferType bufferType;
    MemType type;
    void *hostPtr;
};

enum class ExternalAllocType : uint32_t
{
    CUDA,
    HOST
};

} // namespace mem

} // namespace cupva

#endif