cupva_types.h

Fully qualified name: src/include/cupva_types.h

File members: src/include/cupva_types.h

/*
 * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef CUPVA_TYPES_H
#define CUPVA_TYPES_H

#include <stdint.h>

// default circular buffer line-pitch factor and extra pixels
#define CIRCULAR_BUFFER_LINE_PITCH_FACTOR0 3
#define CIRCULAR_BUFFER_LINE_PITCH_FACTOR1 5
#define CIRCULAR_BUFFER_LINE_PITCH_ALIGNED(size) ((((size) + 1U) / 2U) * 2U)
#define CIRCULAR_BUFFER_EXTRA_BYTES 64
#define CIRCULAR_BUFFER_ALIGNED_SIZE(size) ((((size) + 63U) / 64U) * 64U)

// Horizontal offset and line pitch alignment.
#define TRANSPOSE_MODE_VAL(mode) (1U << ((mode) - 1U))
#define TRANSPOSE_HORIZONTAL_OFFSET(mode, bpp) \
    ((((mode) == 1U) && ((bpp) == 1U)) ? 2U : ((TRANSPOSE_MODE_VAL(mode)) * (bpp)))
#define APPLY_TRANSPOSE_ALIGNMENT(linePitch, mode, bpp)                                    \
    (((((((linePitch) - TRANSPOSE_HORIZONTAL_OFFSET((mode), (bpp))) + 63U) / 64U) * 64U) + \
      TRANSPOSE_HORIZONTAL_OFFSET((mode), (bpp))))
#define TRANSPOSE_LINE_PITCH_ALIGNED(linePitch, mode, bpp) \
    (((mode) == TRANS_MODE_NONE) ? (linePitch) : APPLY_TRANSPOSE_ALIGNMENT((linePitch), (mode), (bpp)))

// DynamicStream related macros
#define DDF_ENTRY_NUM_PER_DESC 6U
#define DDF_ENTRY_HEAD 2U
#define DDF_SCRATCH_PITCH 17U
#define DDF_HIDDEN_HEAD 16U
#define DDF_ALIGN_64B(NUM) (((NUM) + (16U - 1U)) / 16U * 16U)
#define DDF_MAX_NODE_CNT 4U

// scalar table
#define DDF_VPUC_TBL_SIZE(NODE_NUM) DDF_ALIGN_64B(2U * DDF_ENTRY_NUM_PER_DESC * (NODE_NUM) + DDF_ENTRY_HEAD)
#define DDF_TBL_SIZE_IMPL(NODE_NUM) (2U * DDF_VPUC_TBL_SIZE(NODE_NUM) + DDF_HIDDEN_HEAD)
// Size of metadata preceding VPUC table
#define DDF_METADATA_SIZE(nodesPerLane) ((DDF_VPUC_TBL_SIZE((nodesPerLane))) + DDF_HIDDEN_HEAD)

// vector table
#define DDF_PARALLEL_TRANSPOSE_VPUC_TBL_SIZE(NODE_NUM) \
    DDF_ALIGN_64B((2U * DDF_ENTRY_NUM_PER_DESC * (NODE_NUM) + DDF_ENTRY_HEAD) * DDF_SCRATCH_PITCH)
#define DDF_PARALLEL_VPUC_TBL_SIZE(NODE_NUM, LANE_NUM) ((LANE_NUM) * DDF_VPUC_TBL_SIZE(NODE_NUM))
#define DDF_PARALLEL_TBL_SIZE_IMPL(NODE_NUM, LANE_NUM)                                                     \
    (DDF_PARALLEL_VPUC_TBL_SIZE((NODE_NUM), (LANE_NUM)) + DDF_PARALLEL_TRANSPOSE_VPUC_TBL_SIZE(NODE_NUM) + \
     DDF_HIDDEN_HEAD)
// Size of metadata preceding VPUC table for parallel DDF
#define DDF_PARALLEL_METADATA_SIZE(nodesPerLane) \
    ((DDF_PARALLEL_TRANSPOSE_VPUC_TBL_SIZE((nodesPerLane))) + DDF_HIDDEN_HEAD)

// Maximum number of tiles per trigger.
#define GSDF_MAX_NUM_TILES (32U)

// VMEM superbank width in bytes.
#define VMEM_SUPERBANK_WIDTH_IN_BYTES (64U)

/*
 * Maximum number of image planes allowed.
 */
#define GSDF_MAX_NUM_PLANES (8u)

enum DDFItem
{
    // enum constants for storing DDF source address
    DDF_SRC_ADDR = 0,
    // enum constants for storing DDF destination address
    DDF_DST_ADDR = 1,
    // enum constants for storing DDF Tile control
    DDF_TILE_CNTL = 2,
    // enum constants for storing DDF Transfer control
    DDF_TRANS_CNTL = 3,
    // enum constants for storing DDF LP control
    DDF_LP_CNTL = 4,
    // enum constants for storing DDF Description control
    DDF_DESCR_CNTL = 5,
};

struct RasterDataFlowTrigInst
{
    uint8_t gpio;
    int8_t jmpOffst;
    uint8_t trigRpt;
    uint8_t jmpCnt;
};

// Number of instructions
#define RDF_INST_COUNT 6U

// Masks for transferProperties field
#define RDF_TRANSFER_PROPERTIES_IS_READ 7U : 7U
#define RDF_TRANSFER_PROPERTIES_BPPLOG2 6U : 5U
#define RDF_TRANSFER_PROPERTIES_LAYOUT 1U : 0U

struct RasterDataFlowHandler
{
    uint8_t pc;
    uint8_t trigCnt;
    uint8_t gpioHistory;
    struct RasterDataFlowTrigInst trigProgram[RDF_INST_COUNT];
    uint8_t transferProperties;
    int32_t adv[2];
    int32_t cbLen;
    uint16_t linePitch;
    uint16_t nxm1;
    uint16_t ixAdv;
};

struct UnifiedRDFHandler
{
    struct RasterDataFlowHandler hdl;
    void *base;
    uint32_t tileOffset;
    uint32_t deferTrig;
    uint32_t deferSync;
    uint32_t nextTrig;
    uint32_t nextSync;
    void *cbDst;
};

struct DDFParams
{
    uint32_t deadbeef;
    uint32_t ddfTblInternalOfst;
    uint32_t trigger;
    uint8_t laneNum;
    uint8_t nodeNumPerLane;
    uint8_t alignment[50];
};

struct DDFPayload
{
    // Variable for storing src addr of 1D DDF node
    uint32_t ddfSrcAddr[2];
    // Variable for storing dst addr of 1D DDF node
    uint32_t ddfDstAddr[2];
    // Variable for storing tile control word of 1D DDF node
    uint32_t ddfTileCntl[2];
    // variable for storing trans control word of 1D DDF node
    uint32_t ddfTransCntl[2];
    // variable for storing line pitch control word of 1D DDF node
    uint32_t ddfLpCntl[2];
    // variable for storing descr word of 1D DDF node
    uint32_t ddfDescrCntl[2];
};

struct DDFTransposePayload
{
    uint32_t ddfSrcAddr[2 * DDF_SCRATCH_PITCH];
    uint32_t ddfDstAddr[2 * DDF_SCRATCH_PITCH];
    uint32_t ddfTileCntl[2 * DDF_SCRATCH_PITCH];
    uint32_t ddfTransCntl[2 * DDF_SCRATCH_PITCH];
    uint32_t ddfLpCntl[2 * DDF_SCRATCH_PITCH];
    uint32_t ddfDescrCntl[2 * DDF_SCRATCH_PITCH];
};

struct DDFTable
{
    struct DDFParams ddfHeaders;
    uint32_t ddfPayloadHeader[2];
    struct DDFPayload ddfPayload[DDF_MAX_NODE_CNT];
};

struct DDFParallelTable
{
    struct DDFParams ddfHeaders;
    uint32_t ddfPayloadHeader[2 * DDF_SCRATCH_PITCH];
    struct DDFTransposePayload ddfPayload[DDF_MAX_NODE_CNT];
};

struct PvaVpuInstanceData
{
    uint16_t vpu_id;
    uint16_t ppe_task_launched;
    uint32_t vmem_base;
    uint32_t dma_descriptor_base;
    uint32_t l2ram_base;
    uint32_t l2ram_size;
};

struct VmemExportStruct
{
    uint32_t vmemType;
    uint32_t addr;
    uint32_t size;
};

// Specifies whether ExtMemPointer is an L2 type pointer.
#define CUPVA_EXT_MEM_TYPE_L2 (1U)

struct IovaWithFlags
{
    uint32_t addrLo;
    uint8_t addrHi;
    uint8_t reserved[2];
    uint8_t flags;
};

union ExtMemIova
{
    struct IovaWithFlags iova;
    uint64_t val;
};

struct ExtMemPointer
{
    uint64_t base;
    uint64_t offset;
    uint64_t size;
};

typedef struct ExtMemPointer VPUSymbolPointerData;

struct VPUSurfaceMetadata
{
    uint32_t linePitch;
    uint32_t widthInBytes;
    uint32_t height;
    uint8_t format;
    uint8_t blockHeightLog2;
    uint8_t alignment[2];
};

struct VPUSurfaceData
{
    struct ExtMemPointer pointer;
    struct VPUSurfaceMetadata metadata;
};

struct PlanarGeometry
{
    uint16_t widths[GSDF_MAX_NUM_PLANES];
    uint16_t heights[GSDF_MAX_NUM_PLANES];
    uint16_t linePitches[GSDF_MAX_NUM_PLANES];
    uint32_t planeOffsets[GSDF_MAX_NUM_PLANES];
    uint8_t numPlanes;
    uint8_t padding[15];
};

struct GSDFParamsHWSeq
{
    uint32_t triggerAtClose;
    uint32_t hwSeqOffset;
    uint8_t headDid;
    uint8_t chanID;
    uint8_t padding[6];
};

struct GSDFVPUConfigPair
{
    uint32_t value;
    uint32_t address;
};

#define GSDF_SWSEQ_MAX_CHANNEL_COUNT 8U
#define GSDF_NUM_ENTRY_PER_DESC 6U
#define GSDF_SWSEQ_VPUC_TBL_ENTRIES(NODES_PER_CHANNEL) (GSDF_NUM_ENTRY_PER_DESC * (NODES_PER_CHANNEL))
#define GSDF_SWSEQ_VPUC_TBL_STRIDE(NODES_PER_CHANNEL) \
    ((GSDF_SWSEQ_VPUC_TBL_ENTRIES((NODES_PER_CHANNEL)) + 1U) * (uint32_t)sizeof(GSDFVPUConfigPair))

struct GSDFParamsSWSeq
{
    uint8_t headDidTable[GSDF_SWSEQ_MAX_CHANNEL_COUNT];
    uint8_t numChannels;
    uint8_t nodesPerChannel;
    uint8_t padding[6];
};

struct GSDFParams
{
    uint32_t trigger;
    uint16_t tileWidth;
    uint16_t tileHeight;
    uint8_t extIsRaw;
    uint8_t extFmt;
    uint8_t extTransMode;
    uint8_t blockHeightLog2;
    uint8_t isRead;
    uint8_t numTilesPerTrigger;
    uint8_t bpp;
    uint8_t bpe;
    uint8_t useHwseq;
    uint8_t padding[7];
    uint8_t didTable[GSDF_MAX_NUM_TILES];
    struct PlanarGeometry geometry;
    union
    {
        struct GSDFParamsHWSeq hwSeq;
        struct GSDFParamsSWSeq swSeq;
    } sequencing;
};

#define TDF_NUM_SLICES 2

struct TensorDataFlowParams
{
    uint32_t tilePlaneSize;
    uint32_t tileDepth[TDF_NUM_SLICES];
    uint32_t niterHW;
    uint8_t numSlices;
};

enum DmaTransferModeType
{
    DMA_TRANS_MODE_INV = 0,
    DMA_TRANS_MODE_DRAM = 1,
    DMA_TRANS_MODE_VMEM = 2,
    DMA_TRANS_MODE_SRAM = 3,
    DMA_TRANS_MODE_MMIO = 5,
    DMA_TRANS_MODE_VPUCFG = 7
};

enum VmemBufferTypes
{
    VMEM_TYPE_MIN = 0,
    VMEM_TYPE_DATA = 1,
    VMEM_TYPE_VPUC_TABLE = 2,
    VMEM_TYPE_POINTER = 3,
    VMEM_TYPE_SYSTEM = 4,
    VMEM_TYPE_POINTER_EX = 5,
    VMEM_TYPE_MAX = 6,
};

enum TranspositionMode
{
    TRANS_MODE_NONE = 0U,
    TRANS_MODE_1 = 1U,
    TRANS_MODE_2 = 2U,
    TRANS_MODE_4 = 3U,
    TRANS_MODE_8 = 4U,
    TRANS_MODE_16 = 5U,
    TRANS_MODE_32 = 6U,
};

struct PvaDmaDescriptor
{
    uint32_t DESCR_CNTL;
    uint32_t SRC_ADR;
    uint32_t DST_ADR;
    uint32_t TILE_CNTL;
    uint32_t LP_CNTL;
    uint32_t SRCPT1_CNTL;
    uint32_t DSTPT1_CNTL;
    uint32_t SRCPT2_CNTL;
    uint32_t DSTPT2_CNTL;
    uint32_t SRCPT3_CNTL;
    uint32_t DSTPT3_CNTL;
    uint32_t BFSTART_CNTL;
    uint32_t BFSIZE_CNTL;
    uint32_t EVENT_CNTL;
    uint32_t TRANS_CNTL;
    uint32_t NDTM_CNTL;
};

#define PVA_DMA_DESC_DESCR_CNTL_0_DSTM_RANGE 2U : 0U
#define PVA_DMA_DESC_DESCR_CNTL_0_SRC_TF_RANGE 3U : 3U
#define PVA_DMA_DESC_DESCR_CNTL_0_DDTM_RANGE 6U : 4U
#define PVA_DMA_DESC_DESCR_CNTL_0_DST_TF_RANGE 7U : 7U
#define PVA_DMA_DESC_DESCR_CNTL_0_LINK_DID_RANGE 15U : 8U
#define PVA_DMA_DESC_DESCR_CNTL_0_SRC_ADDR1_RANGE 23U : 16U
#define PVA_DMA_DESC_DESCR_CNTL_0_DST_ADDR1_RANGE 31U : 24U

#define PVA_DMA_DESC_SRC_ADR_0_SRC_ADDR0_RANGE 31U : 0U

#define PVA_DMA_DESC_DST_ADR_0_DST_ADDR0_RANGE 31U : 0U

#define PVA_DMA_DESC_TILE_CNTL_0_TX_RANGE 15U : 0U
#define PVA_DMA_DESC_TILE_CNTL_0_TY_RANGE 31U : 16U

#define PVA_DMA_DESC_LP_CNTL_0_SLP_ADV_RANGE 15U : 0U
#define PVA_DMA_DESC_LP_CNTL_0_DLP_ADV_RANGE 31U : 16U

#define PVA_DMA_DESC_SRCPT1_CNTL_0_ST1_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_SRCPT1_CNTL_0_NS1_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_DSTPT1_CNTL_0_DT1_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_DSTPT1_CNTL_0_ND1_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_SRCPT2_CNTL_0_ST2_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_SRCPT2_CNTL_0_NS2_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_DSTPT2_CNTL_0_DT2_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_DSTPT2_CNTL_0_ND2_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_SRCPT3_CNTL_0_ST3_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_SRCPT3_CNTL_0_NS3_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_DSTPT3_CNTL_0_DT3_ADV_RANGE 23U : 0U
#define PVA_DMA_DESC_DSTPT3_CNTL_0_ND3_ADV_RANGE 31U : 24U

#define PVA_DMA_DESC_BFSTART_CNTL_0_SB_START_RANGE 15U : 0U
#define PVA_DMA_DESC_BFSTART_CNTL_0_DB_START_RANGE 31U : 16U

#define PVA_DMA_DESC_BFSIZE_CNTL_0_SB_SIZE_RANGE 15U : 0U
#define PVA_DMA_DESC_BFSIZE_CNTL_0_DB_SIZE_RANGE 31U : 16U

#define PVA_DMA_DESC_EVENT_CNTL_0_TRIG_CH_EVENTS_RANGE 15U : 0U
#define PVA_DMA_DESC_EVENT_CNTL_0_ECET_RANGE 17U : 16U
#define PVA_DMA_DESC_EVENT_CNTL_0_TRIG_VPU_HW_EVENTS_RANGE 21U : 18U
#define PVA_DMA_DESC_EVENT_CNTL_0_TRIG_MISC_HW_EVENTS_RANGE 24U : 22U
#define PVA_DMA_DESC_EVENT_CNTL_0_TRIG_SW_EVENTS_RANGE 27U : 25U
#define PVA_DMA_DESC_EVENT_CNTL_0_DSCLOAD_RANGE 28U : 28U
#define PVA_DMA_DESC_EVENT_CNTL_0_PRTM_RANGE 31U : 30U

#define PVA_DMA_DESC_TRANS_CNTL_0_PX_RANGE 7U : 0U
#define PVA_DMA_DESC_TRANS_CNTL_0_PY_RANGE 15U : 8U
#define PVA_DMA_DESC_TRANS_CNTL_0_BPP_RANGE 17U : 16U
#define PVA_DMA_DESC_TRANS_CNTL_0_PXDIR_RANGE 18U : 18U
#define PVA_DMA_DESC_TRANS_CNTL_0_PYDIR_RANGE 19U : 19U
#define PVA_DMA_DESC_TRANS_CNTL_0_BPE_RANGE 20U : 20U
#define PVA_DMA_DESC_TRANS_CNTL_0_TTS_RANGE 21U : 21U
#define PVA_DMA_DESC_TRANS_CNTL_0_RSVD_RANGE 22U : 22U
#define PVA_DMA_DESC_TRANS_CNTL_0_ITC_RANGE 23U : 23U
#define PVA_DMA_DESC_TRANS_CNTL_0_PREFEN_RANGE 24U : 24U
#define PVA_DMA_DESC_TRANS_CNTL_0_DCBM_RANGE 25U : 25U
#define PVA_DMA_DESC_TRANS_CNTL_0_SCBM_RANGE 26U : 26U
#define PVA_DMA_DESC_TRANS_CNTL_0_SBADR_RANGE 31U : 27U

#define PVA_DMA_DESC_NDTM_CNTL_0_SB_STARTUB_RANGE 1U : 0U
#define PVA_DMA_DESC_NDTM_CNTL_0_DB_STARTUB_RANGE 3U : 2U
#define PVA_DMA_DESC_NDTM_CNTL_0_SB_SIZEUB_RANGE 5U : 4U
#define PVA_DMA_DESC_NDTM_CNTL_0_DB_SIZEUB_RANGE 7U : 6U
#define PVA_DMA_DESC_NDTM_CNTL_0_RSVD_RANGE 15U : 8U
#define PVA_DMA_DESC_NDTM_CNTL_0_FRDA_RANGE 31U : 16U

#define CUPVA_FIELD_SHIFT(x)                ((int32_t)(false?x)%32)
#define CUPVA_FIELD_SHIFT_UNSIGNED(x)       ((false?x)%32U)
#define CUPVA_FIELD_MASK(x)                 (0xFFFFFFFFU>>(31U-((true?x)%32U)+((false?x)%32U)))
#define CUPVA_FIELD(x, val) (((val) & CUPVA_FIELD_MASK(x)) << (CUPVA_FIELD_SHIFT_UNSIGNED(x)))
#define CUPVA_EXTRACT_FIELD(x, val) (((val) >> CUPVA_FIELD_SHIFT_UNSIGNED(x)) & CUPVA_FIELD_MASK(x))

#define CUPVA_DMA_FIELD(r, f, value) CUPVA_FIELD(PVA_DMA_DESC_##r##_0_##f##_RANGE, value)

enum BufferLayoutTypes
{
    DEFAULT_LAYOUT = 0,
    SINGLE_LAYOUT,
    DOUBLE_LAYOUT,
    CIRCULAR_LAYOUT
};

#define SEQUENCE_DATAFLOW_MAX_TRANSFERS 8U

struct SequenceDataFlowTransferInfo
{
    uint8_t link_did;
    uint8_t desc_id;
};

struct SequenceDataFlowParameters
{
    uint32_t cfg_trig;
    uint32_t data_trig;
    uint32_t trigger_count;
    struct SequenceDataFlowTransferInfo transfers[SEQUENCE_DATAFLOW_MAX_TRANSFERS];
    uint8_t config_id;
    uint8_t xfer0_trigger;
    uint8_t reserved[1];
};

#endif