dma_common.h#
Fully qualified name: src/device/vpu_runtime/include/cupva_device/impl/dma_common.h
File members: src/device/vpu_runtime/include/cupva_device/impl/dma_common.h
/*
* Copyright (c) 2023 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an express
* license agreement from NVIDIA Corporation is strictly prohibited.
*/
#ifndef DMA_COMMON_H
#define DMA_COMMON_H
#include <cupva_types.h>
#define CUPVA_DESC_DSTM_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_DSTM_RANGE)
#define CUPVA_DESC_DDTM_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_DDTM_RANGE)
#define CUPVA_DESC_LINK_DID_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_LINK_DID_RANGE)
#define CUPVA_DESC_SRC_ADDR1_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_SRC_ADDR1_RANGE)
#define CUPVA_DESC_DST_ADDR1_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_DST_ADDR1_RANGE)
#define CUPVA_DESC_SRC_TF_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_SRC_TF_RANGE)
#define CUPVA_DESC_DST_TF_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DESCR_CNTL_0_DST_TF_RANGE)
#define CUPVA_DESC_SRC_ADR_0_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_SRC_ADR_0_SRC_ADDR0_RANGE)
#define CUPVA_DESC_DST_ADR_0_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DST_ADR_0_DST_ADDR0_RANGE)
#define CUPVA_DESC_TX_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TILE_CNTL_0_TX_RANGE)
#define CUPVA_DESC_TY_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TILE_CNTL_0_TY_RANGE)
#define CUPVA_DESC_SRC_LP_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_LP_CNTL_0_SLP_ADV_RANGE)
#define CUPVA_DESC_DST_LP_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_LP_CNTL_0_DLP_ADV_RANGE)
#define CUPVA_DESC_PX_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_PX_RANGE)
#define CUPVA_DESC_PY_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_PY_RANGE)
#define CUPVA_DESC_PXDIR_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_PXDIR_RANGE)
#define CUPVA_DESC_PYDIR_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_PYDIR_RANGE)
#define CUPVA_DESC_SBADR_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_SBADR_RANGE)
#define CUPVA_DESC_ITC_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_ITC_RANGE)
#define CUPVA_DESC_BPP_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_BPP_RANGE)
#define CUPVA_DESC_NS1_ADV_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_SRCPT1_CNTL_0_NS1_ADV_RANGE)
#define CUPVA_DESC_ND1_ADV_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_DSTPT1_CNTL_0_ND1_ADV_RANGE)
#define CUPVA_DESC_BPE_SHIFT CUPVA_FIELD_SHIFT(PVA_DMA_DESC_TRANS_CNTL_0_BPE_RANGE)
#define CUPVA_DMA_DESC_CLEAR_MASK(x) ((uint32_t) ~(CUPVA_FIELD_MASK(x) << CUPVA_FIELD_SHIFT(x)))
#define CUPVA_DESC_DSTM_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DSTM_RANGE)
#define CUPVA_DESC_DDTM_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DDTM_RANGE)
#define CUPVA_DESC_LINK_DID_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_LINK_DID_RANGE)
#define CUPVA_DESC_SRC_ADDR1_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_SRC_ADDR1_RANGE)
#define CUPVA_DESC_DST_ADDR1_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DST_ADDR1_RANGE)
#define CUPVA_DESC_SRC_TF_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_SRC_TF_RANGE)
#define CUPVA_DESC_DST_TF_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DST_TF_RANGE)
#define CUPVA_DESC_SRC_ADR_0_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_SRC_ADR_0_SRC_ADDR0_RANGE)
#define CUPVA_DESC_DST_ADR_0_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_DST_ADR_0_DST_ADDR0_RANGE)
#define CUPVA_DESC_TX_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TILE_CNTL_0_TX_RANGE)
#define CUPVA_DESC_TY_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TILE_CNTL_0_TY_RANGE)
#define CUPVA_DESC_SRC_LP_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_LP_CNTL_0_SLP_ADV_RANGE)
#define CUPVA_DESC_DST_LP_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_LP_CNTL_0_DLP_ADV_RANGE)
#define CUPVA_DESC_PX_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_PX_RANGE)
#define CUPVA_DESC_PY_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_PY_RANGE)
#define CUPVA_DESC_PXDIR_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_PXDIR_RANGE)
#define CUPVA_DESC_PYDIR_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_PYDIR_RANGE)
#define CUPVA_DESC_SBADR_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_SBADR_RANGE)
#define CUPVA_DESC_ITC_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_ITC_RANGE)
#define CUPVA_DESC_BPP_CLEAR_MASK CUPVA_DMA_DESC_CLEAR_MASK(PVA_DMA_DESC_TRANS_CNTL_0_BPP_RANGE)
#define CUPVA_DESC_SRC_ADDR1_MASK CUPVA_FIELD_MASK(PVA_DMA_DESC_DESCR_CNTL_0_SRC_ADDR1_RANGE)
#define CUPVA_DESC_DST_ADDR1_MASK CUPVA_FIELD_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DST_ADDR1_RANGE)
#define CUPVA_DESC_SRC_TF_MASK CUPVA_FIELD_MASK(PVA_DMA_DESC_DESCR_CNTL_0_SRC_TF_RANGE)
#define CUPVA_DESC_DST_TF_MASK CUPVA_FIELD_MASK(PVA_DMA_DESC_DESCR_CNTL_0_DST_TF_RANGE)
#define CUPVA_DESC_SBADR_MASK CUPVA_FIELD_MASK(PVA_DMA_DESC_TRANS_CNTL_0_SBADR_RANGE)
#define CUPVA_DMA_DESC_EXTRACT(r, f, value) \
(((value) >> CUPVA_FIELD_SHIFT(PVA_DMA_DESC_##r##_0_##f##_RANGE)) & \
CUPVA_FIELD_MASK(PVA_DMA_DESC_##r##_0_##f##_RANGE))
#define CUPVA_DMA_DESC_OFFSET(field) ((uint32_t)offsetof(PvaDmaDescriptor, field))
// VPU ICACHE base address and offset.
#if (CUPVA_PVA_GEN_NUMBER < 3)
# define CUPVA_ICACHE_VPU0_BASE 0x48000U
#else
# define CUPVA_ICACHE_VPU0_BASE 0x44000U
#endif
#define CUPVA_ICACHE_VPU_OFFSET 0x10000U
#define CUPVA_ICACHE_BASE (CUPVA_ICACHE_VPU0_BASE + CUPVA_ICACHE_VPU_OFFSET * cupvaGetVpuId())
#define CUPVA_ICACHE_PREFETCH_CMD_STATUS (CUPVA_ICACHE_BASE + 0x10U)
#define CUPVA_ICACHE_PREFETCH_START (CUPVA_ICACHE_BASE + 0x14U)
#define CUPVA_ICACHE_VPU_PREFETCH_CMD_STATUS_0_GO_RANGE 0U : 0U
#define CUPVA_ICACHE_VPU_PREFETCH_CMD_STATUS_0_LEN_RANGE 15U : 8U
// DMA channel base address and channel aperture size.
#define CUPVA_DMA0_CHAN_BASE 0xA0000
#define CUPVA_DMA1_CHAN_BASE 0xD0000
#define CUPVA_DMA_CHAN_APERTURE_SIZE 0x2000
// HWSEQFSCNTL register offset
#define CUPVA_DMA_CHAN_HWSEQFSCNTL_OFFSET 0x94
// CUPVA user channel starting index.
#define CUPVA_DMA_CHAN_USER_SIDX (1)
// DMA HWSEQ ram offset (6144U)
#define CUPVA_DMA_HWSEQ_RAM_OFFSET (0x1800U)
// Max padding value supported by DMA
#define CUPVA_MAX_PADDING (0xFF)
#endif // CUPVA_DMA_COMMON_H