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CPU-Specific Details#

This chapter summarizes the CPU layout of RTX Spark CPUs.

RTX Spark CPU Configuration#

The RTX Spark family of products consists of two CPU SKUs. One with 18-cores and one with 20-cores. All of them have two sets of ARM CPU cores: Cortex-X925 for the highest performance and Cortex-A725 for better performance-efficiency. The high-end NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU) has 20 cores: 10 P (performance) and 10 E (efficiency) cores. Other variants may have different core counts, for example NVIDIA RTX Spark N1X (5120-core Blackwell RTX GPU) features nine performance and nine efficiency cores. Developers should pay attention to ordering of the CPU cores, which is returned by Windows GetLogicalProcessorInformationEx() API. Unlike many other CPUs with the heterogenous cores, where the cores are sorted such that all the performance cores are enumerated first followed by all the efficiency cores, N1 CPUs report the core layout differently.

RTX Spark Core Layout#

There are two important considerations regarding the Windows CPU enumeration order:

  • RTX Spark has two core clusters, both including performance and efficiency cores.

  • For each cluster, the API will list efficiency cores first followed by the performance cores.

  • E cores and P cores: On NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU), each cluster consists of E (Efficiency) cores and P (Performance) cores, which are interleaved in 5-core clusters.

  • Interleave order: On NVIDIA RTX Spark N1X (6144-core Blackwell RTX GPU), the E cores and P cores are interleaved in the order E P E P. The affinity mask of the 10 E cores is 0x07C1F and the affinity mask of the 10 P cores is 0xF83E0.

E-core mask 0x07C1F = 0000 0111 1100 0001 1111
P-core mask 0xF83E0 = 1111 1000 0011 1110 0000

If you logically OR the two masks, you get a complete 0xFFFFF corresponding to the total of 20 cores.

Summary#

When adapting your workloads to work best on CPUs with heterogenous cores – one should not assume specific layout and/or ordering of cores. Instead, rely on checking the EfficiencyClass member of the SYSTEM_CPU_SET_INFORMATION structure returned by the OS for each CPU core, and do not stop enumeration after observing a change in the EfficiencyClass of later cores. This is true not only for RTX Spark CPUs, but also for heterogeneous CPUs from other vendors. Implementations making incorrect assumptions about the core layout and failing to correctly identify counts and locations of the cores with different efficiency classes may suffer unintended performance issues. In most scenarios, however, applications should avoid pinning threads. Instead, they can use thread priorities and process QoS to control scheduling.