2.3. Field Value Enums
Classes
Defines
- #define NVML_FI_DEV_ECC_CURRENT 1
- Current ECC mode. 1=Active. 0=Inactive.
- #define NVML_FI_DEV_ECC_DBE_AGG_CBU 28
- CBU double bit aggregate ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_DEV 23
- Device memory double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_L1 19
- L1 cache double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_L2 21
- L2 cache double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_REG 25
- Register File double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_TEX 27
- Texture memory double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6
- Total double bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_CBU 17
- CBU double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_DEV 12
- Device memory double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_L1 8
- L1 cache double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_L2 10
- L2 cache double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_REG 14
- Register file double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_TEX 16
- Texture memory double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4
- Total double bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_PENDING 2
- Pending ECC mode. 1=Active. 0=Inactive.
- #define NVML_FI_DEV_ECC_SBE_AGG_DEV 22
- Device memory single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_AGG_L1 18
- L1 cache single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_AGG_L2 20
- L2 cache single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_AGG_REG 24
- Register File single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_AGG_TEX 26
- Texture memory single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5
- Total single bit aggregate (persistent) ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_DEV 11
- Device memory single bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_L1 7
- L1 cache single bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_L2 9
- L2 cache single bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_REG 13
- Register file single bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_TEX 15
- Texture memory single bit volatile ECC errors.
- #define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3
- Total single bit volatile ECC errors.
- #define NVML_FI_DEV_MEMORY_TEMP 82
- Memory temperature for the device.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60
- NVLink Bandwidth Counter for Counter Set 0, Lane 0.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61
- NVLink Bandwidth Counter for Counter Set 0, Lane 1.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L10 124
- NVLink Bandwidth Counter for Counter Set 0, Lane 10.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L11 125
- NVLink Bandwidth Counter for Counter Set 0, Lane 11.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62
- NVLink Bandwidth Counter for Counter Set 0, Lane 2.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63
- NVLink Bandwidth Counter for Counter Set 0, Lane 3.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64
- NVLink Bandwidth Counter for Counter Set 0, Lane 4.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65
- NVLink Bandwidth Counter for Counter Set 0, Lane 5.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L6 120
- NVLink Bandwidth Counter for Counter Set 0, Lane 6.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L7 121
- NVLink Bandwidth Counter for Counter Set 0, Lane 7.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L8 122
- NVLink Bandwidth Counter for Counter Set 0, Lane 8.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L9 123
- NVLink Bandwidth Counter for Counter Set 0, Lane 9.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66
- NVLink Bandwidth Counter Total for Counter Set 0, All Lanes.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67
- NVLink Bandwidth Counter for Counter Set 1, Lane 0.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68
- NVLink Bandwidth Counter for Counter Set 1, Lane 1.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L10 130
- NVLink Bandwidth Counter for Counter Set 1, Lane 10.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L11 131
- NVLink Bandwidth Counter for Counter Set 1, Lane 11.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69
- NVLink Bandwidth Counter for Counter Set 1, Lane 2.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70
- NVLink Bandwidth Counter for Counter Set 1, Lane 3.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71
- NVLink Bandwidth Counter for Counter Set 1, Lane 4.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72
- NVLink Bandwidth Counter for Counter Set 1, Lane 5.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L6 126
- NVLink Bandwidth Counter for Counter Set 1, Lane 6.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L7 127
- NVLink Bandwidth Counter for Counter Set 1, Lane 7.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L8 128
- NVLink Bandwidth Counter for Counter Set 1, Lane 8.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L9 129
- NVLink Bandwidth Counter for Counter Set 1, Lane 9.
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73
- NVLink Bandwidth Counter Total for Counter Set 1, All Lanes.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39
- NVLink data CRC Error Counter for Lane 0.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40
- NVLink data CRC Error Counter for Lane 1.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 106
- NVLink data CRC Error Counter for Lane 10.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 107
- NVLink data CRC Error Counter for Lane 11.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41
- NVLink data CRC Error Counter for Lane 2.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42
- NVLink data CRC Error Counter for Lane 3.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43
- NVLink data CRC Error Counter for Lane 4.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44
- NVLink data CRC Error Counter for Lane 5.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 102
- NVLink data CRC Error Counter for Lane 6.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 103
- NVLink data CRC Error Counter for Lane 7.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 104
- NVLink data CRC Error Counter for Lane 8.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 105
- NVLink data CRC Error Counter for Lane 9.
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45
- NvLink data CRC Error Counter total for all Lanes.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32
- NVLink flow control CRC Error Counter for Lane 0.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33
- NVLink flow control CRC Error Counter for Lane 1.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 100
- NVLink flow control CRC Error Counter for Lane 10.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 101
- NVLink flow control CRC Error Counter for Lane 11.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34
- NVLink flow control CRC Error Counter for Lane 2.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35
- NVLink flow control CRC Error Counter for Lane 3.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36
- NVLink flow control CRC Error Counter for Lane 4.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37
- NVLink flow control CRC Error Counter for Lane 5.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 96
- NVLink flow control CRC Error Counter for Lane 6.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 97
- NVLink flow control CRC Error Counter for Lane 7.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 98
- NVLink flow control CRC Error Counter for Lane 8.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 99
- NVLink flow control CRC Error Counter for Lane 9.
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38
- NVLink flow control CRC Error Counter total for all Lanes.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 148
- NVLink data ECC Error Counter for Link 0.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 149
- NVLink data ECC Error Counter for Link 1.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 158
- NVLink data ECC Error Counter for Link 10.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 159
- NVLink data ECC Error Counter for Link 11.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 150
- NVLink data ECC Error Counter for Link 2.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 151
- NVLink data ECC Error Counter for Link 3.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 152
- NVLink data ECC Error Counter for Link 4.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 153
- NVLink data ECC Error Counter for Link 5.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 154
- NVLink data ECC Error Counter for Link 6.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 155
- NVLink data ECC Error Counter for Link 7.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 156
- NVLink data ECC Error Counter for Link 8.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 157
- NVLink data ECC Error Counter for Link 9.
- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL 160
- NvLink data ECC Error Counter total for all Links.
- #define NVML_FI_DEV_NVLINK_LINK_COUNT 91
- Number of NVLinks present on the device.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53
- NVLink Recovery Error Counter for Lane 0.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54
- NVLink Recovery Error Counter for Lane 1.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 118
- NVLink Recovery Error Counter for Lane 10.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 119
- NVLink Recovery Error Counter for Lane 11.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55
- NVLink Recovery Error Counter for Lane 2.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56
- NVLink Recovery Error Counter for Lane 3.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57
- NVLink Recovery Error Counter for Lane 4.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58
- NVLink Recovery Error Counter for Lane 5.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 114
- NVLink Recovery Error Counter for Lane 6.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 115
- NVLink Recovery Error Counter for Lane 7.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 116
- NVLink Recovery Error Counter for Lane 8.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 117
- NVLink Recovery Error Counter for Lane 9.
- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59
- NVLink Recovery Error Counter total for all Lanes.
- #define NVML_FI_DEV_NVLINK_REMOTE_NVLINK_ID 146
- Remote device NVLink ID.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46
- NVLink Replay Error Counter for Lane 0.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47
- NVLink Replay Error Counter for Lane 1.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 112
- NVLink Replay Error Counter for Lane 10.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 113
- NVLink Replay Error Counter for Lane 11.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48
- NVLink Replay Error Counter for Lane 2.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49
- NVLink Replay Error Counter for Lane 3.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50
- NVLink Replay Error Counter for Lane 4.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51
- NVLink Replay Error Counter for Lane 5.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 108
- NVLink Replay Error Counter for Lane 6.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 109
- NVLink Replay Error Counter for Lane 7.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 110
- NVLink Replay Error Counter for Lane 8.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 111
- NVLink Replay Error Counter for Lane 9.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52
- NVLink Replay Error Counter total for all Lanes.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON 90
- Common NVLink Speed in MBps for active links.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L0 84
- NVLink Speed in MBps for Link 0.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L1 85
- NVLink Speed in MBps for Link 1.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L10 136
- NVLink Speed in MBps for Link 10.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L11 137
- NVLink Speed in MBps for Link 11.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L2 86
- NVLink Speed in MBps for Link 2.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L3 87
- NVLink Speed in MBps for Link 3.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L4 88
- NVLink Speed in MBps for Link 4.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L5 89
- NVLink Speed in MBps for Link 5.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L6 132
- NVLink Speed in MBps for Link 6.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L7 133
- NVLink Speed in MBps for Link 7.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L8 134
- NVLink Speed in MBps for Link 8.
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L9 135
- NVLink Speed in MBps for Link 9.
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX 139
- NVLink RX Data throughput in KiB.
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX 138
- NVLink TX Data throughput in KiB.
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX 141
- NVLink RX Data + protocol overhead in KiB.
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX 140
- NVLink TX Data + protocol overhead in KiB.
- #define NVML_FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT 147
- Number of NVLinks connected to NVSwitch.
- #define NVML_FI_DEV_PCIE_REPLAY_COUNTER 94
- PCIe replay counter.
- #define NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER 95
- PCIe replay rollover counter.
- #define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77
- Perf Policy Counter for Board Limit.
- #define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78
- Perf Policy Counter for Low GPU Utilization Policy.
- #define NVML_FI_DEV_PERF_POLICY_POWER 74
- Perf Policy Counter for Power Policy.
- #define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79
- Perf Policy Counter for Reliability Policy.
- #define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76
- Perf Policy Counter for Sync boost Policy.
- #define NVML_FI_DEV_PERF_POLICY_THERMAL 75
- Perf Policy Counter for Thermal Policy.
- #define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80
- Perf Policy Counter for Total App Clock Policy.
- #define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81
- Perf Policy Counter for Total Base Clocks Policy.
- #define NVML_FI_DEV_REMAPPED_COR 142
- Number of remapped rows due to correctable errors.
- #define NVML_FI_DEV_REMAPPED_FAILURE 145
- If any rows failed to be remapped 1=yes 0=no.
- #define NVML_FI_DEV_REMAPPED_PENDING 144
- If any rows are pending remapping. 1=yes 0=no.
- #define NVML_FI_DEV_REMAPPED_UNC 143
- Number of remapped rows due to uncorrectable errors.
- #define NVML_FI_DEV_RETIRED_DBE 30
- Number of retired pages because of double bit errors.
- #define NVML_FI_DEV_RETIRED_PENDING 31
- If any pages are pending retirement. 1=yes. 0=no.
- #define NVML_FI_DEV_RETIRED_PENDING_DBE 93
- If any pages are pending retirement due to DBE. 1=yes. 0=no.
- #define NVML_FI_DEV_RETIRED_PENDING_SBE 92
- If any pages are pending retirement due to SBE. 1=yes. 0=no.
- #define NVML_FI_DEV_RETIRED_SBE 29
- Number of retired pages because of single bit errors.
- #define NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION 83
- Total energy consumption for the GPU in mJ since the driver was last reloaded.
- #define NVML_FI_MAX 161
- One greater than the largest field ID defined above.
Defines
- #define NVML_FI_DEV_ECC_CURRENT 1
-
Field Identifiers.
All Identifiers pertain to a device. Each ID is only used once and is guaranteed never to change.
- #define NVML_FI_DEV_ECC_DBE_AGG_CBU 28
-
- #define NVML_FI_DEV_ECC_DBE_AGG_DEV 23
-
- #define NVML_FI_DEV_ECC_DBE_AGG_L1 19
-
- #define NVML_FI_DEV_ECC_DBE_AGG_L2 21
-
- #define NVML_FI_DEV_ECC_DBE_AGG_REG 25
-
- #define NVML_FI_DEV_ECC_DBE_AGG_TEX 27
-
- #define NVML_FI_DEV_ECC_DBE_AGG_TOTAL 6
-
- #define NVML_FI_DEV_ECC_DBE_VOL_CBU 17
-
- #define NVML_FI_DEV_ECC_DBE_VOL_DEV 12
-
- #define NVML_FI_DEV_ECC_DBE_VOL_L1 8
-
- #define NVML_FI_DEV_ECC_DBE_VOL_L2 10
-
- #define NVML_FI_DEV_ECC_DBE_VOL_REG 14
-
- #define NVML_FI_DEV_ECC_DBE_VOL_TEX 16
-
- #define NVML_FI_DEV_ECC_DBE_VOL_TOTAL 4
-
- #define NVML_FI_DEV_ECC_PENDING 2
-
- #define NVML_FI_DEV_ECC_SBE_AGG_DEV 22
-
- #define NVML_FI_DEV_ECC_SBE_AGG_L1 18
-
- #define NVML_FI_DEV_ECC_SBE_AGG_L2 20
-
- #define NVML_FI_DEV_ECC_SBE_AGG_REG 24
-
- #define NVML_FI_DEV_ECC_SBE_AGG_TEX 26
-
- #define NVML_FI_DEV_ECC_SBE_AGG_TOTAL 5
-
- #define NVML_FI_DEV_ECC_SBE_VOL_DEV 11
-
- #define NVML_FI_DEV_ECC_SBE_VOL_L1 7
-
- #define NVML_FI_DEV_ECC_SBE_VOL_L2 9
-
- #define NVML_FI_DEV_ECC_SBE_VOL_REG 13
-
- #define NVML_FI_DEV_ECC_SBE_VOL_TEX 15
-
- #define NVML_FI_DEV_ECC_SBE_VOL_TOTAL 3
-
- #define NVML_FI_DEV_MEMORY_TEMP 82
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L0 60
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L1 61
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L10 124
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L11 125
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L2 62
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L3 63
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L4 64
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L5 65
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L6 120
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L7 121
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L8 122
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_L9 123
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C0_TOTAL 66
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L0 67
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L1 68
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L10 130
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L11 131
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L2 69
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L3 70
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L4 71
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L5 72
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L6 126
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L7 127
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L8 128
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_L9 129
-
- #define NVML_FI_DEV_NVLINK_BANDWIDTH_C1_TOTAL 73
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L0 39
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L1 40
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L10 106
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L11 107
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L2 41
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L3 42
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L4 43
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L5 44
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L6 102
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L7 103
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L8 104
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_L9 105
-
- #define NVML_FI_DEV_NVLINK_CRC_DATA_ERROR_COUNT_TOTAL 45
-
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L0 32
-
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L1 33
-
- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L10 100
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L11 101
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L2 34
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L3 35
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L4 36
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L5 37
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L6 96
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L7 97
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L8 98
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_L9 99
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- #define NVML_FI_DEV_NVLINK_CRC_FLIT_ERROR_COUNT_TOTAL 38
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L0 148
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L1 149
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L10 158
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L11 159
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L2 150
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L3 151
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L4 152
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L5 153
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L6 154
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L7 155
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L8 156
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_L9 157
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- #define NVML_FI_DEV_NVLINK_ECC_DATA_ERROR_COUNT_TOTAL 160
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- #define NVML_FI_DEV_NVLINK_LINK_COUNT 91
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L0 53
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L1 54
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L10 118
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L11 119
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L2 55
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L3 56
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L4 57
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L5 58
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L6 114
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L7 115
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L8 116
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_L9 117
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- #define NVML_FI_DEV_NVLINK_RECOVERY_ERROR_COUNT_TOTAL 59
-
- #define NVML_FI_DEV_NVLINK_REMOTE_NVLINK_ID 146
-
Remote device NVLink ID
Link ID needs to be specified in the scopeId field in nvmlFieldValue_t.
- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L0 46
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L1 47
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L10 112
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L11 113
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L2 48
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L3 49
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L4 50
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L5 51
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L6 108
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L7 109
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L8 110
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_L9 111
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- #define NVML_FI_DEV_NVLINK_REPLAY_ERROR_COUNT_TOTAL 52
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_COMMON 90
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L0 84
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- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L1 85
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L10 136
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- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L11 137
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L2 86
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- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L3 87
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L4 88
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L5 89
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L6 132
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L7 133
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L8 134
-
- #define NVML_FI_DEV_NVLINK_SPEED_MBPS_L9 135
-
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_RX 139
-
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_DATA_TX 138
-
NVLink throughput counters field values
Link ID needs to be specified in the scopeId field in nvmlFieldValue_t. A scopeId of UINT_MAX returns aggregate value summed up across all links for the specified counter type in fieldId.
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_RX 141
-
- #define NVML_FI_DEV_NVLINK_THROUGHPUT_RAW_TX 140
-
- #define NVML_FI_DEV_NVSWITCH_CONNECTED_LINK_COUNT 147
-
NVSwitch: connected NVLink count
- #define NVML_FI_DEV_PCIE_REPLAY_COUNTER 94
-
- #define NVML_FI_DEV_PCIE_REPLAY_ROLLOVER_COUNTER 95
-
- #define NVML_FI_DEV_PERF_POLICY_BOARD_LIMIT 77
-
- #define NVML_FI_DEV_PERF_POLICY_LOW_UTILIZATION 78
-
- #define NVML_FI_DEV_PERF_POLICY_POWER 74
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- #define NVML_FI_DEV_PERF_POLICY_RELIABILITY 79
-
- #define NVML_FI_DEV_PERF_POLICY_SYNC_BOOST 76
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- #define NVML_FI_DEV_PERF_POLICY_THERMAL 75
-
- #define NVML_FI_DEV_PERF_POLICY_TOTAL_APP_CLOCKS 80
-
- #define NVML_FI_DEV_PERF_POLICY_TOTAL_BASE_CLOCKS 81
-
- #define NVML_FI_DEV_REMAPPED_COR 142
-
- #define NVML_FI_DEV_REMAPPED_FAILURE 145
-
- #define NVML_FI_DEV_REMAPPED_PENDING 144
-
- #define NVML_FI_DEV_REMAPPED_UNC 143
-
- #define NVML_FI_DEV_RETIRED_DBE 30
-
- #define NVML_FI_DEV_RETIRED_PENDING 31
-
- #define NVML_FI_DEV_RETIRED_PENDING_DBE 93
-
- #define NVML_FI_DEV_RETIRED_PENDING_SBE 92
-
- #define NVML_FI_DEV_RETIRED_SBE 29
-
- #define NVML_FI_DEV_TOTAL_ENERGY_CONSUMPTION 83
-
- #define NVML_FI_MAX 161
-