Clocks
This chapter describes how to configure clock sources.
For information about available Tegra clock sources and capabilities, see the “Clock and Reset Controller” section of the Tegra Technical Reference Manual (TRM) for your chip. This section of the TRM also describes clock sources muxes and provides descriptions of available clock sources for each component.
For information on using sysfs to get or set clock information, see
Clock Settings for Tegra Parker in
Sysfs and Procfs Entries.
Changing Clock Frequencies
In general, each block/module has a dedicated clock source register that provides clock source and clock divider control to that device. For detailed information of the specified register, see the discussion of CLK_RST_CONTROLLER_CLK_COURCE_<module_name> in the TRM, where <module_name> is the name of the block or module. The divider is typically 8 bits which consist of 7 integer bits and 1 fractional bit (U7.1).
Note: | Before changing clock values or clock source for the MCM chip, consult the VCM 3.1 design guide if applicable to your platform and the appropriate NVIDIA datasheet. |
To change the default clock configuration for Tegra code-name Parker
For information, see “Changing the Default Clock Configuration in Configuring Power on BPMP Firmware (Tegra Parker)” in the NVIDIA DRIVE Foundation SDK 5.0 DRIVE Platform Development Guide.
To change clock configurations in the kernel device driver module for Tegra code-name Parker
For information see the Common Clock Framework described in
<top>/drive-oss-src/kernel/Documentation/clk.txt.
Note: | The A01 board for codename Parker exhibits frequency issues. Consequently, the CPU/GPU/SOC clocks may not achieve their maximum frequencies. Maximum frequency limits vary with the chip manufacturing process. |
