nvrm_gpu.h

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/*
 * Copyright (c) 2014-2018 NVIDIA Corporation.  All rights reserved.
 *
 * NVIDIA Corporation and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA Corporation is strictly prohibited.
 */

#ifndef INCLUDED_nvrm_gpu_H
#define INCLUDED_nvrm_gpu_H

#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>

#include "nvcommon.h"
#include "nverror.h"

#if defined(__cplusplus)
extern "C"
{
#endif

typedef struct NvRmGpuLibRec NvRmGpuLib;
typedef struct NvRmGpuDeviceRec NvRmGpuDevice;

/**** Generic functions ****/

typedef struct NvRmGpuLibOpenAttrRec
{
    // placeholder for extensions
    uint32_t reserved;

} NvRmGpuLibOpenAttr;

#define NVRM_GPU_DEFINE_LIB_OPEN_ATTR(x) \
    NvRmGpuLibOpenAttr x = { 0 }

NvRmGpuLib *NvRmGpuLibOpen(const NvRmGpuLibOpenAttr *attr);

NvError NvRmGpuLibClose(NvRmGpuLib *hlib);

typedef enum
{
    NvRmGpuLibDeviceState_Detached,
    NvRmGpuLibDeviceState_Attached,
} NvRmGpuDeviceState;

typedef struct NvRmGpuLibDeviceListEntryRec
{
    int deviceIndex;
    NvRmGpuDeviceState deviceState;
    const char *name; // temporary name, e.g., Nouveau GPU 0 or some such
} NvRmGpuLibDeviceListEntry;

const NvRmGpuLibDeviceListEntry *NvRmGpuLibListDevices(NvRmGpuLib *hlib, size_t *pnumDevices);

NvError NvRmGpuLibAttachDevice(NvRmGpuLib *const hlib, const int deviceIndex);

NvError NvRmGpuLibDetachDevice(NvRmGpuLib *const hlib, const int deviceIndex);

/**** Device functions ****/

#define NVRM_GPU_DEVICE_INDEX_DEFAULT (-1)

typedef enum
{
    NvRmGpuSyncType_Default,       // platform-specific default
    NvRmGpuSyncType_SyncFd,
    NvRmGpuSyncType_Syncpoint,
} NvRmGpuSyncType;

typedef struct NvRmGpuDeviceOpenAttrRec
{
    NvRmGpuSyncType syncType;

    bool sandboxFriendlyChannels;
} NvRmGpuDeviceOpenAttr;

#define NVRM_GPU_DEFINE_DEVICE_OPEN_ATTR(x) \
    NvRmGpuDeviceOpenAttr x = { NvRmGpuSyncType_Default, false }


NvError NvRmGpuDeviceOpen(NvRmGpuLib *hLib, int deviceIndex, const NvRmGpuDeviceOpenAttr *attr,
                          NvRmGpuDevice **phDevice);

NvError NvRmGpuDeviceClose(NvRmGpuDevice *hDevice);

#if NVOS_IS_LINUX || NVOS_IS_QNX
#define NVRM_GPU_CLOCK_ASYNC_REQ_HANDLE_PRIFMT "d"
typedef int NvRmGpuClockAsyncReqHandle;
#else
#define NVRM_GPU_CLOCK_ASYNC_REQ_HANDLE_PRIFMT "p"
typedef struct NvRmGpuClockAsyncNotImplemented *NvRmGpuClockAsyncReqHandle;
#endif

typedef enum NvRmGpuClockDomain
{
    NvRmGpuClockDomain_MCLK = 0,    
    NvRmGpuClockDomain_GPCCLK,      
    NvRmGpuClockDomain_Count
} NvRmGpuClockDomain;

typedef enum NvRmGpuClockType
{
    NvRmGpuClockType_Target = 1,    
    NvRmGpuClockType_Actual,        
    NvRmGpuClockType_Effective      
} NvRmGpuClockType;

typedef struct NvRmGpuClockGetEntryRec
{
    NvRmGpuClockDomain domain;      
    NvRmGpuClockType type;          
    uint64_t freqHz;                
} NvRmGpuClockGetEntry;

typedef struct NvRmGpuClockSetEntryRec
{
    NvRmGpuClockDomain domain;
    uint64_t freqHz;
} NvRmGpuClockSetEntry;

typedef struct NvRmGpuClockRangeRec
{
    uint64_t minHz;
    uint64_t maxHz;
} NvRmGpuClockRange;

typedef struct NvRmGpuClockPointRec
{
    uint64_t freqHz;
} NvRmGpuClockPoint;

typedef struct NvRmGpuClockDomainInfoRec
{
    NvRmGpuClockDomain domain;
    NvRmGpuClockRange range;
    size_t maxVfPoints;
} NvRmGpuClockDomainInfo;

NvError NvRmGpuClockGetDomains(NvRmGpuDevice *hDevice,
                               const NvRmGpuClockDomainInfo **infos,
                               size_t *pNumDomains);

NvError NvRmGpuClockGetPoints(NvRmGpuDevice *hDevice,
                              NvRmGpuClockDomain domain,
                              NvRmGpuClockPoint *pClkPoints,
                              size_t *pNumPoints);

NvError NvRmGpuClockSet(NvRmGpuDevice *hDevice,
                        const NvRmGpuClockSetEntry *pClkSetEntries,
                        size_t numEntries,
                        NvRmGpuClockAsyncReqHandle *phReq);

NvError NvRmGpuClockWaitAsyncReq(NvRmGpuDevice *hDevice,
                                 const NvRmGpuClockAsyncReqHandle *phReqs,
                                 size_t numEntries,
                                 uint32_t timeoutMs);

NvError NvRmGpuClockCloseAsyncReq(NvRmGpuDevice *hDevice,
                                  NvRmGpuClockAsyncReqHandle hReq);

NvError NvRmGpuClockWaitAnyEvent(NvRmGpuDevice *hDevice,
                                 uint32_t timeoutMs);

NvError NvRmGpuClockGet(NvRmGpuDevice *hDevice,
                        NvRmGpuClockGetEntry *pClkGetEntries,
                        size_t numEntries);

typedef enum
{
    NvRmGpuDeviceVoltage_Core = 1,
    NvRmGpuDeviceVoltage_SRAM,
    NvRmGpuDeviceVoltage_Bus
} NvRmGpuDeviceVoltage;

NvError NvRmGpuDeviceListVoltageSensors(NvRmGpuDevice *hDevice,
                                        const NvRmGpuDeviceVoltage **pSensors,
                                        size_t *numSensors);
NvError NvRmGpuDeviceGetVoltage(NvRmGpuDevice *hDevice,
                                NvRmGpuDeviceVoltage which,
                                uint64_t *pVoltageMicroVolt);

typedef enum
{
    NvRmGpuDeviceCurrent_Bus = 1,
} NvRmGpuDeviceCurrent;

NvError NvRmGpuDeviceListCurrentSensors(NvRmGpuDevice *hDevice,
                                        const NvRmGpuDeviceCurrent **pSensors,
                                        size_t *numSensors);

NvError NvRmGpuDeviceGetCurrent(NvRmGpuDevice *hDevice,
                                NvRmGpuDeviceCurrent which,
                                uint64_t *pCurrentMicroAmpere);

typedef enum
{
    NvRmGpuDevicePower_Bus = 1  // power consumed at regulator
} NvRmGpuDevicePower;

NvError NvRmGpuDeviceListPowerSensors(NvRmGpuDevice *hDevice,
                                      const NvRmGpuDevicePower **pSensors,
                                      size_t *numSensors);

NvError NvRmGpuDeviceGetPower(NvRmGpuDevice *hDevice,
                              NvRmGpuDevicePower which,
                              uint64_t *pPowerMicroWatt);


typedef enum
{
    NvRmGpuDeviceTemperature_InternalSensor = 1
} NvRmGpuDeviceTemperature;

NvError NvRmGpuDeviceListTemperatureSensors(NvRmGpuDevice *hDevice,
                                            const NvRmGpuDeviceTemperature **pSensors,
                                            size_t *numSensors);

NvError NvRmGpuDeviceGetTemperature(NvRmGpuDevice *hDevice,
                                    NvRmGpuDeviceTemperature which,
                                    int32_t *pTemperatureMilliCelsius);

NvError NvRmGpuDeviceThermalAlertSetLimit(NvRmGpuDevice *hDevice,
                                          int32_t temperature_mC);

typedef enum
{
    NvRmGpuDeviceEventId_VfUpdate = 0,
    NvRmGpuDeviceEventId_AlarmTargetVfNotPossible,
    NvRmGpuDeviceEventId_AlarmLocalTargetVfNotPossible,
    NvRmGpuDeviceEventId_AlarmClockArbiterFailed,
    NvRmGpuDeviceEventId_AlarmVfTableUpdateFailed,
    NvRmGpuDeviceEventId_AlarmThermalAboveThreshold,
    NvRmGpuDeviceEventId_AlarmPowerAboveThreshold,
    NvRmGpuDeviceEventId_AlarmGpuLost,
    NvRmGpuDeviceEventId_Count
} NvRmGpuDeviceEventId;

typedef struct NvRmGpuDeviceEventSessionRec NvRmGpuDeviceEventSession;

typedef struct NvRmGpuDeviceEventSessionOpenAttrRec
{
    const NvRmGpuDeviceEventId *filterList;
    size_t filterListSize;
} NvRmGpuDeviceEventSessionOpenAttr;

#define NVRM_GPU_DEFINE_DEVICE_EVENT_SESSION_ATTR(x)            \
    NvRmGpuDeviceEventSessionOpenAttr x = { NULL, 0 }

static inline void NvRmGpuDeviceEventSessionOpenAttrSetAllEvents(NvRmGpuDeviceEventSessionOpenAttr *attr)
{
    static const NvRmGpuDeviceEventId allEvents[] =
    {
        NvRmGpuDeviceEventId_VfUpdate,
        NvRmGpuDeviceEventId_AlarmTargetVfNotPossible,
        NvRmGpuDeviceEventId_AlarmLocalTargetVfNotPossible,
        NvRmGpuDeviceEventId_AlarmClockArbiterFailed,
        NvRmGpuDeviceEventId_AlarmVfTableUpdateFailed,
        NvRmGpuDeviceEventId_AlarmThermalAboveThreshold,
        NvRmGpuDeviceEventId_AlarmPowerAboveThreshold,
        NvRmGpuDeviceEventId_AlarmGpuLost
    };
    attr->filterList = allEvents;
    attr->filterListSize = NV_ARRAY_SIZE(allEvents);
}

NvError NvRmGpuDeviceEventSessionOpen(NvRmGpuDevice *hDevice,
                                      const NvRmGpuDeviceEventSessionOpenAttr *attr,
                                      NvRmGpuDeviceEventSession **phSession);

typedef struct NvRmGpuDeviceEventInfoRec
{
    NvRmGpuDeviceEventId eventId;
    uint64_t timeNs;    // GPU timestamp in ns
} NvRmGpuDeviceEventInfo;

NvError NvRmGpuDeviceEventSessionRead(NvRmGpuDeviceEventSession *hSession,
                                      NvRmGpuDeviceEventInfo *pEventInfo,
                                      uint32_t timeoutMs);

NvError NvRmGpuDeviceEventSessionClose(NvRmGpuDeviceEventSession *hSession);

#if defined(__cplusplus)
}
#endif

#if !defined(NV_SDK_BUILD)
#include "nvrm_gpu_priv.h"
#endif

#endif