nvmedia_tensormetadata.h

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/*
 * Copyright (c) 2017 - 2020, NVIDIA CORPORATION.  All rights reserved.  All
 * information contained herein is proprietary and confidential to NVIDIA
 * Corporation.  Any use, reproduction, or disclosure without the written
 * permission of NVIDIA Corporation is prohibited.
 */
 
#ifndef NVM_TENSORMETADATA_H
#define NVM_TENSORMETADATA_H
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define NVMEDIA_TENSOR_MAX_DIMENSIONS                       (8u)
 
#define NVM_TENSOR_ATTR_DIMENSION_ORDER_NHWC                (0x00000001u)
 
#define NVM_TENSOR_ATTR_DIMENSION_ORDER_NCHW                (0x00000002u)
 
#define NVM_TENSOR_ATTR_DIMENSION_ORDER_NCxHWx              (0x00000003u)
 
#if (NV_IS_SAFETY == 0)
 
#define NVM_TENSOR_ATTR_DATA_TYPE_UINT                      (0x00000001u)
#endif
 
#define NVM_TENSOR_ATTR_DATA_TYPE_INT                       (0x00000002u)
 
#define NVM_TENSOR_ATTR_DATA_TYPE_FLOAT                     (0x00000003u)
 
#if (NV_IS_SAFETY == 0)
 
#define NVM_TENSOR_ATTR_BITS_PER_ELEMENT_64                 (64U)
 
#define NVM_TENSOR_ATTR_BITS_PER_ELEMENT_32                 (32U)
#endif /* (NV_IS_SAFETY == 0) */
 
#define NVM_TENSOR_ATTR_BITS_PER_ELEMENT_16                 (16U)
 
#define NVM_TENSOR_ATTR_BITS_PER_ELEMENT_8                  (8U)
 
#if (NV_IS_SAFETY == 0)
 
#define NVM_TENSOR_NHWC_E_STRIDE_INDEX         0U
 
#define NVM_TENSOR_NHWC_C_STRIDE_INDEX         NVM_TENSOR_NHWC_E_STRIDE_INDEX
 
#define NVM_TENSOR_NHWC_W_STRIDE_INDEX         1U
 
#define NVM_TENSOR_NHWC_H_STRIDE_INDEX         2U
 
#define NVM_TENSOR_NHWC_N_STRIDE_INDEX         3U
 
#define NVM_TENSOR_NCHW_E_STRIDE_INDEX         0U
 
#define NVM_TENSOR_NCHW_W_STRIDE_INDEX         NVM_TENSOR_NCHW_E_STRIDE_INDEX
 
#define NVM_TENSOR_NCHW_H_STRIDE_INDEX         1U
 
#define NVM_TENSOR_NCHW_C_STRIDE_INDEX         2U
 
#define NVM_TENSOR_NCHW_N_STRIDE_INDEX         3U
 
#define NVM_TENSOR_NCxHWx_E_STRIDE_INDEX       0U
 
#define NVM_TENSOR_NCxHWx_X_STRIDE_INDEX       NVM_TENSOR_NCxHWx_E_STRIDE_INDEX
 
#define NVM_TENSOR_NCxHWx_W_STRIDE_INDEX       1U
 
#define NVM_TENSOR_NCxHWx_H_STRIDE_INDEX       2U
 
#define NVM_TENSOR_NCxHWx_Cx_STRIDE_INDEX      3U
 
#define NVM_TENSOR_NCxHWx_N_STRIDE_INDEX       4U
 
#define NVM_TENSOR_NHWC_C_DIMSZ_INDEX          0U
 
#define NVM_TENSOR_NHWC_W_DIMSZ_INDEX          1U
 
#define NVM_TENSOR_NHWC_H_DIMSZ_INDEX          2U
 
#define NVM_TENSOR_NHWC_N_DIMSZ_INDEX          3U
 
#define NVM_TENSOR_NCHW_W_DIMSZ_INDEX          0U
 
#define NVM_TENSOR_NCHW_H_DIMSZ_INDEX          1U
 
#define NVM_TENSOR_NCHW_C_DIMSZ_INDEX          2U
 
#define NVM_TENSOR_NCHW_N_DIMSZ_INDEX          3U
 
#define NVM_TENSOR_NCxHWx_x_DIMSZ_INDEX        0U
 
#define NVM_TENSOR_NCxHWx_W_DIMSZ_INDEX        1U
 
#define NVM_TENSOR_NCxHWx_H_DIMSZ_INDEX        2U
 
#define NVM_TENSOR_NCxHWx_Cx_DIMSZ_INDEX       3U
 
#define NVM_TENSOR_NCxHWx_N_DIMSZ_INDEX        4U
 
#endif /* (NV_IS_SAFETY == 0) */
 
typedef struct {
    uint32_t dimsNum;
    uint32_t dimSizes[NVMEDIA_TENSOR_MAX_DIMENSIONS];
    uint32_t dimstrides[NVMEDIA_TENSOR_MAX_DIMENSIONS];
    uint32_t dimsOrder;
    uint32_t bitsPerElement;
    uint32_t dataType;
    uint32_t attrib4D_N;
    uint32_t attrib4D_C;
    uint32_t attrib4D_H;
    uint32_t attrib4D_W;
    uint32_t attrib4D_X;
} NvMediaTensorMetaData;
 
#ifdef __cplusplus
};     /* extern "C" */
#endif
 
#endif /* NVM_TENSORMETADATA_H */