nvrm_gpu.h

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/*
 * Copyright (c) 2014-2019 NVIDIA Corporation.  All rights reserved.
 *
 * NVIDIA Corporation and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA Corporation is strictly prohibited.
 */
 
#ifndef INCLUDED_nvrm_gpu_H
#define INCLUDED_nvrm_gpu_H
 
#include <stdbool.h>
#include <stdint.h>
#include <stddef.h>
 
#include "nvcommon.h"
#include "nverror.h"
 
#if defined(__cplusplus)
extern "C"
{
#endif
 
#if defined(NVRM_GPU_BUILD_VARIANT)
namespace nvrm_gpu
{
#endif
 
#if defined(NVRM_GPU_UNIT_TEST_BUILD) && (NVRM_GPU_UNIT_TEST_BUILD)
#define NVRM_GPU_ATTR_NAMESPACE(x) ::nvrm_gpu::x
#else
#define NVRM_GPU_ATTR_NAMESPACE(x) x
#endif
 
 
// -------------------------------------------------
// --------------- API Groups ----------------------
// -------------------------------------------------
 
 
 
 
 
 
// -------------------------------------------------
// --------------- Handles -------------------------
// -------------------------------------------------
 
typedef struct NvRmGpuLibRec NvRmGpuLib;
 
typedef struct NvRmGpuDeviceRec NvRmGpuDevice;
 
typedef struct NvRmGpuDeviceEventSessionRec NvRmGpuDeviceEventSession;
 
 
// -------------------------------------------------
// --------------- Library functions ---------------
// -------------------------------------------------
 
typedef struct NvRmGpuLibOpenAttrRec
{
    uint32_t reserved;
 
} NvRmGpuLibOpenAttr;
 
#define NVRM_GPU_DEFINE_LIB_OPEN_ATTR(x) \
    NVRM_GPU_ATTR_NAMESPACE(NvRmGpuLibOpenAttr) x = { 0U }
 
NvRmGpuLib *NvRmGpuLibOpen(const NvRmGpuLibOpenAttr *attr);
 
NvError NvRmGpuLibClose(NvRmGpuLib *hLib);
 
typedef enum
{
    NvRmGpuLibDeviceState_Attached,
 
    NvRmGpuLibDeviceState_Detached,
 
    NvRmGpuLibDeviceState_InsufficientPrivileges,
 
    NvRmGpuLibDeviceState_Unknown,
 
} NvRmGpuLibDeviceState;
 
 
typedef struct NvRmGpuLibDeviceListEntryRec
{
    int deviceIndex;
 
    NvRmGpuLibDeviceState deviceState;
 
    bool hasDeviceStateControl;
 
    const char *name;
} NvRmGpuLibDeviceListEntry;
 
const NvRmGpuLibDeviceListEntry *NvRmGpuLibListDevices(NvRmGpuLib *hLib, size_t *pNumDevices);
 
NvError NvRmGpuLibAttachDevice(NvRmGpuLib *hLib, int deviceIndex);
 
NvError NvRmGpuLibDetachDevice(NvRmGpuLib *hLib, int deviceIndex);
 
 
#define NVRM_GPU_DEVICE_INDEX_DEFAULT (-1)
 
typedef enum
{
    NvRmGpuSyncType_Default,
 
    NvRmGpuSyncType_SyncFd,
 
    NvRmGpuSyncType_Syncpoint,
} NvRmGpuSyncType;
 
 
typedef struct NvRmGpuDeviceOpenAttrRec
{
    NvRmGpuSyncType syncType;
 
    bool sandboxFriendlyChannels;
} NvRmGpuDeviceOpenAttr;
 
#define NVRM_GPU_DEFINE_DEVICE_OPEN_ATTR(x) \
    NVRM_GPU_ATTR_NAMESPACE(NvRmGpuDeviceOpenAttr) x = { NVRM_GPU_ATTR_NAMESPACE(NvRmGpuSyncType_Default), false }
 
 
NvError NvRmGpuDeviceOpen(NvRmGpuLib *hLib, int deviceIndex, const NvRmGpuDeviceOpenAttr *attr,
                          NvRmGpuDevice **phDevice);
 
NvError NvRmGpuDeviceClose(NvRmGpuDevice *hDevice);
 
 
#if NVOS_IS_LINUX || NVOS_IS_QNX
 
#define NVRM_GPU_CLOCK_ASYNC_REQ_HANDLE_PRIFMT "d"
 
typedef int NvRmGpuClockAsyncReqHandle;
#else
 
#define NVRM_GPU_CLOCK_ASYNC_REQ_HANDLE_PRIFMT "p"
 
typedef struct NvRmGpuClockAsyncNotImplemented *NvRmGpuClockAsyncReqHandle;
#endif
 
typedef enum
{
    NvRmGpuClockDomain_MCLK = 0,
 
    NvRmGpuClockDomain_GPCCLK,
 
    NvRmGpuClockDomain_Count
} NvRmGpuClockDomain;
 
typedef enum NvRmGpuClockType
{
    NvRmGpuClockType_Target = 1,
 
    NvRmGpuClockType_Actual = 2,
 
    NvRmGpuClockType_Effective = 3
} NvRmGpuClockType;
 
 
typedef struct NvRmGpuClockGetEntryRec
{
    NvRmGpuClockDomain domain;
 
    NvRmGpuClockType type;
 
    uint64_t freqHz;
 
} NvRmGpuClockGetEntry;
 
typedef struct NvRmGpuClockSetEntryRec
{
    NvRmGpuClockDomain domain;
 
    uint64_t freqHz;
} NvRmGpuClockSetEntry;
 
typedef struct NvRmGpuClockRangeRec
{
    uint64_t minHz;
    uint64_t maxHz;
} NvRmGpuClockRange;
 
typedef struct NvRmGpuClockPointRec
{
    uint64_t freqHz;
} NvRmGpuClockPoint;
 
typedef struct NvRmGpuClockDomainInfoRec
{
    NvRmGpuClockDomain domain;
 
    NvRmGpuClockRange range;
 
    size_t maxVfPoints;
 
} NvRmGpuClockDomainInfo;
 
NvError NvRmGpuClockGetDomains(NvRmGpuDevice *hDevice,
                               const NvRmGpuClockDomainInfo **infos,
                               size_t *pNumDomains);
 
NvError NvRmGpuClockGetPoints(NvRmGpuDevice *hDevice,
                              NvRmGpuClockDomain domain,
                              NvRmGpuClockPoint *pClkPoints,
                              size_t *pNumPoints);
 
NvError NvRmGpuClockSet(NvRmGpuDevice *hDevice,
                        const NvRmGpuClockSetEntry *pClkSetEntries,
                        size_t numEntries,
                        NvRmGpuClockAsyncReqHandle *phReq);
 
NvError NvRmGpuClockWaitAsyncReq(NvRmGpuDevice *hDevice,
                                 const NvRmGpuClockAsyncReqHandle *phReqs,
                                 size_t numEntries,
                                 uint32_t timeoutMs);
 
 
NvError NvRmGpuClockCloseAsyncReq(NvRmGpuDevice *hDevice,
                                  NvRmGpuClockAsyncReqHandle hReq);
 
 
NvError NvRmGpuClockWaitAnyEvent(NvRmGpuDevice *hDevice,
                                 uint32_t timeoutMs);
 
 
NvError NvRmGpuClockGet(NvRmGpuDevice *hDevice,
                        NvRmGpuClockGetEntry *pClkGetEntries,
                        size_t numEntries);
 
typedef enum
{
    NvRmGpuDeviceVoltage_Core = 1,
 
    NvRmGpuDeviceVoltage_SRAM,
 
    NvRmGpuDeviceVoltage_Bus
} NvRmGpuDeviceVoltage;
 
NvError NvRmGpuDeviceListVoltageSensors(NvRmGpuDevice *hDevice,
                                        const NvRmGpuDeviceVoltage **pSensors,
                                        size_t *pNumSensors);
 
 
NvError NvRmGpuDeviceGetVoltage(NvRmGpuDevice *hDevice,
                                NvRmGpuDeviceVoltage which,
                                uint64_t *pVoltageMicroVolt);
 
typedef enum
{
    NvRmGpuDeviceCurrent_Bus = 1,
} NvRmGpuDeviceCurrent;
 
 
NvError NvRmGpuDeviceListCurrentSensors(NvRmGpuDevice *hDevice,
                                        const NvRmGpuDeviceCurrent **pSensors,
                                        size_t *pNumSensors);
 
NvError NvRmGpuDeviceGetCurrent(NvRmGpuDevice *hDevice,
                                NvRmGpuDeviceCurrent which,
                                uint64_t *pCurrentMicroAmpere);
 
typedef enum
{
    NvRmGpuDevicePower_Bus = 1
} NvRmGpuDevicePower;
 
NvError NvRmGpuDeviceListPowerSensors(NvRmGpuDevice *hDevice,
                                      const NvRmGpuDevicePower **pSensors,
                                      size_t *pNumSensors);
 
NvError NvRmGpuDeviceGetPower(NvRmGpuDevice *hDevice,
                              NvRmGpuDevicePower which,
                              uint64_t *pPowerMicroWatt);
 
 
typedef enum
{
    NvRmGpuDeviceTemperature_InternalSensor = 1
} NvRmGpuDeviceTemperature;
 
NvError NvRmGpuDeviceListTemperatureSensors(NvRmGpuDevice *hDevice,
                                            const NvRmGpuDeviceTemperature **pSensors,
                                            size_t *pNumSensors);
 
NvError NvRmGpuDeviceGetTemperature(NvRmGpuDevice *hDevice,
                                    NvRmGpuDeviceTemperature which,
                                    int32_t *pTemperatureMilliCelsius);
 
NvError NvRmGpuDeviceThermalAlertSetLimit(NvRmGpuDevice *hDevice,
                                          int32_t temperature_mC);
 
 
typedef enum
{
    // @brief Frequency change event
    NvRmGpuDeviceEventId_VfUpdate = 0,
 
    NvRmGpuDeviceEventId_AlarmTargetVfNotPossible,
 
    NvRmGpuDeviceEventId_AlarmLocalTargetVfNotPossible,
 
    NvRmGpuDeviceEventId_AlarmClockArbiterFailed,
 
    NvRmGpuDeviceEventId_AlarmVfTableUpdateFailed,
 
    NvRmGpuDeviceEventId_AlarmThermalAboveThreshold,
 
    NvRmGpuDeviceEventId_AlarmPowerAboveThreshold,
 
    NvRmGpuDeviceEventId_AlarmGpuLost,
 
    NvRmGpuDeviceEventId_Count
 
} NvRmGpuDeviceEventId;
 
typedef struct NvRmGpuDeviceEventSessionOpenAttrRec
{
    const NvRmGpuDeviceEventId *filterList;
 
    size_t filterListSize;
 
} NvRmGpuDeviceEventSessionOpenAttr;
 
#define NVRM_GPU_DEFINE_DEVICE_EVENT_SESSION_ATTR(x)            \
    NVRM_GPU_ATTR_NAMESPACE(NvRmGpuDeviceEventSessionOpenAttr) x = { NULL, 0 }
 
static inline void NvRmGpuDeviceEventSessionOpenAttrSetAllEvents(NvRmGpuDeviceEventSessionOpenAttr *attr)
{
    static const NvRmGpuDeviceEventId allEvents[] =
    {
        NvRmGpuDeviceEventId_VfUpdate,
        NvRmGpuDeviceEventId_AlarmTargetVfNotPossible,
        NvRmGpuDeviceEventId_AlarmLocalTargetVfNotPossible,
        NvRmGpuDeviceEventId_AlarmClockArbiterFailed,
        NvRmGpuDeviceEventId_AlarmVfTableUpdateFailed,
        NvRmGpuDeviceEventId_AlarmThermalAboveThreshold,
        NvRmGpuDeviceEventId_AlarmPowerAboveThreshold,
        NvRmGpuDeviceEventId_AlarmGpuLost
    };
    attr->filterList = allEvents;
    attr->filterListSize = NV_ARRAY_SIZE(allEvents);
}
 
NvError NvRmGpuDeviceEventSessionOpen(NvRmGpuDevice *hDevice,
                                      const NvRmGpuDeviceEventSessionOpenAttr *attr,
                                      NvRmGpuDeviceEventSession **phSession);
 
typedef struct NvRmGpuDeviceEventInfoRec
{
    NvRmGpuDeviceEventId eventId;
 
    uint64_t timeNs;
 
} NvRmGpuDeviceEventInfo;
 
NvError NvRmGpuDeviceEventSessionRead(NvRmGpuDeviceEventSession *hSession,
                                      NvRmGpuDeviceEventInfo *pEventInfo,
                                      uint32_t timeoutMs);
 
NvError NvRmGpuDeviceEventSessionClose(NvRmGpuDeviceEventSession *hSession);
 
#if defined(NVRM_GPU_BUILD_VARIANT)
} // namespace nvrm_gpu
#endif
 
#if defined(__cplusplus)
}
#endif
 
#if !defined(NV_SDK_BUILD)
#include "nvrm_gpu_priv.h"
#endif
 
#endif