NVIDIA Tegra Linux Driver Package

Development Guide
28.3 Release

Overriding Default Clock Rates
Configuring Clocks
NVIDIA® Tegra® Board Support Package (BSP) supports configuring Tegra clocks and peripheral clocks through the software. This topic describes how to check clock status, get maximum rates for clocks, and configure clock sources.
For information about available Tegra clock sources and capabilities, see the “Clock and Reset Controller” section of the Tegra Technical Reference Manual (TRM) for your chip. This section of the TRM also describes clock source multiplexers and provides descriptions of available clock sources for each component.
In kernel 4.4 and following, the common clock framework (CCF) is supported. As a result:
All device drivers use the public CCF APIs include/linux/clk.h, and include/linux/clk-provider.h, including functions such as clk_get, clk_enable, devm_clk_get, clk_prepare_enable, clk_prepare_disable, clk_disable, and others, instead of Tegra specific APIs.
All clock drivers, including the Tegra custom clk driver, implement clk_ops.
Clock sources and clocks required by devices are defined in the Device Tree.
The Tegra custom clock driver is available in the kernel-4.4/drivers/clk/tegra/ directory.
Clock rate and clock source information is available in the following files:
CCF Basic Clocks
Driver File
clk-pll.c, clk-pll-out.c
Audio Sync
Peripheral Gate
cclk-periph.c, clk-periph-fixed.c, clk-periph-gate.c, clk-tegra-periph.c
clk-super.c, clk-tegra-super-gen4.c
Jetson TX1 clocks
Jetson TX2 clocks
To check clock status
On the device, enter the following command to launch debugfs and check the clock:
sudo -s
# cat /sys/kernel/debug/clk/clk_summary
An example of debugfs output for TX1 is as follows.
An example of debugfs output for TX2 is as follows.
Overriding Default Clock Rates
The default clock rate of each component is set during boot and updated under control of the driver or framework in the case of TX1, or BPMP in the case of TX2. The debugfs service provides a way to override the default clock rate and set a fixed clock rate. Use debugfs for debugging and experimental purposes only.
TX1 contains the following clocks, controlled by various frameworks:
/sys/kernel/debug/clk/override.[ape, c3bus, gbus, mselect, abus, c2bus, emc, host1x, sclk]
For example, the GPU clock, i.e., the gbus rate, is under GPU frequency scaling. Change the gbus rate with the following commands:
echo X > /sys/kernel/debug/clk/override.gbus/clk_update_rate
echo 1 > /sys/kernel/debug/clk/override.gbus/clk_state
Re-enable gbus frequency scaling with the following command:
echo 0 > /sys/kernel/debug/clk/override.gbus/clk_state
Valid clock rates can be found using clk_possible_rates. For example, find the rates for gbus with the following command:
cat /sys/kernel/debug/clk/gbus/clk_possible_rates
For other clocks, update clock rates with the following command:
echo x > /sys/kernel/debug/clk/<module>/clk_update_rate
The TX2 clocks are controlled by BPMP. For example, override the EMC rate with the following commands:
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/state
echo x > /sys/kernel/debug/bpmp/debug/clk/emc/rate
Configuring Clocks
In general, each block or module has a dedicated clock source register. For detailed information about a given register, see CLK_RST_CONTROLLER_CLK_SOURCE_<module_name> in the Tegra Technical Reference Manual (TRM).
Clock source registers provide clock source selection and clock divider control for the module. The divider is typically 8 bits, 7 integer bits and 1 fractional bit (U7.1).
To change clock configurations in the kernel device driver module
1. Declare clocks in Device Tree. For example, for padctl-uphy, clocks can be declared as follows:
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>,
<&tegra_car TEGRA210_CLK_USB2_TRK>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "hsic_trk", "usb2_trk", "pll_e";
2. Use the devm_clk_get function to obtain the desired clock source using clock-names.
3. Use the clk_get_parent function to obtain the parent clock for the desired clock.
4. Use the clk_set_parent function to select the specified clock source for the target clock.
5. Use the clk_set_rate function to set the frequency of the target clock.
The divider is calculated automatically according to the target rate. Successful clock frequency settings must meet the available divider of that module and the frequency of the clock source.
6. Use the clk_round_rate function to get the exact clock frequency that can be configured from the current clock source.
7. Use clk_prepare_enable (or clk_prepare and clk_enable) functions to ungate/enable the clock. The clk_prepare function can be used instead of clk_enable to ungate a clock if the operation may sleep.
Some modules may have additional dividers, e.g., DC_DISP_DISP_CLOCK_CONTROL_0.
For more information, see the Tegra Technical Reference Manual (TRM) for your chip.