NVIDIA Tegra
NVIDIA Tegra Linux Driver Package

Development Guide
28.3 Release


 
Design for Debugging
 
DFD Improvements
CoreSight Trace Sinks ETF and ETR
CoreSight AMBA Trace ID (ATID) Mapping
NVIDIA® Tegra® TX1 and TX2 devices leverage the enhancements in the design for debugging (DFD) feature. DFD enables the development and use of debugging tools that allow developers of Tegra-based implementations to place the Tegra TX1 or TX2 processor into known states and trace its behavior while running. Benefits of this enhanced DFD implementation include:
Reduced power leakage
Enhanced security
Availability of standard interfaces
This topic describes the debuggable blocks and their debugging strategies. Use this information to help determine why something may not be working in the software you have developed using NVIDIA® Tegra® Board Support Package (BSP).
The topic also describes the software implementation of the hardware and software features in the Tegra Technical Reference Manual (TRM). Use it as your primary source for information and debugging.
DFD Improvements
The DFD improvements in Tegra TX1 and TX2 devices are as follows.
Hardware DFD Feature
Tegra TX1
Tegra TX2
Improvements
Connection to CPU (JTAG)
Debug Communication Channel with Memory Access Mode in v8
Debug Communication Channel with Memory Access Mode in v8
Faster code download/upload via the debugger.
Connection to AXI-AP (JTAG)
AXI-AP 34 bit address, Can access complete MMIO and DRAM without requiring SMMU
Connection to SNIC allowing complete access to the system
Complete system access when CPUs are powered down, dead, under reset, clock disabled, or unable break in.
Connection to APE (JTAG)
CoreSight
CoreSight
No change.
Connection to BPMP, SPE, and SCE
N/A
CoreSight
Full CoreSight debug is available to the BPMP, SPE, and SCE that is available to the main.
Trace Storage
ETF: 16KB circular buffer
ETF: 32KB circular buffer
Larger buffer for longer duration trace. Preserved through WDT resets.
CoreSight Trace Sinks ETF and ETR
The CoreSight trace sink characteristics for Tegra TX1 and TX2 DFD is as follows. It includes the corresponding Embedded Trace FIFO (ETF), ETR, and USB limits.
Characteristic
ETF (32 KB)
DDR via ETR DMA
USB
Throughput
41.58 Gbps @ 408 MHz and 128 bit
(contact NVIDIA for higher frequency requirements.)
41.58 Gbps
Real time processor tracing requires reduction of CPU frequency.
Intrusive
No
Yes
Yes
Available on Commercial Devices
Yes
Yes
Yes
Use Cases
Collect trace for watchdog reset, and code optimization for the CCPLEX.
Collects trace information for watchdog reset, and code optimization for the CCPLEX (note the high bandwidth requirement at DDR = 25%).
Use for single CPU trace at low frequency, or APE only trace to avoid saturation of DRAM bandwidth
Tracing limited to USB speeds. Use for single CPU trace at low frequency, or APE only trace to avoid saturation of DRAM bandwidth.
CoreSight AMBA Trace ID (ATID) Mapping
The mapping for CoreSight AMBA Trace ID (ATID) is as follows. When collecting trace from multiple sources, the trace sinks (ETF and ETR) use ATIDs to segregate trace data.
BCCPLEX (also called Fast Cluster or Big Cluster) using A57 processors
ATID
Processor
Protocol
0x40
CPU0
ETMv4
0x41
CPU1
ETMv4
0x42
CPU2
ETMv4
0x43
CPU3
ETMv4
APE, Cortex A9
ATID
Processor
Protocol
0x20
CPU0
PFT1.0
STM
ATID
Processor
Protocol
0x10
NA
MIPI STP