NVIDIA Tegra Linux Driver Package

Development Guide
28.3 Release

Display Configuration and Bringup
Setting HDMI or DP Screen Resolution
Mirroring or Extending Displays
Determining Display Timing Values
Configuring the Display Serial Interface
Configuring the Display Port
Configuring Pulse Width Modulation
Hard-coding Kernel Display Boot Mode for HDMI
Panel Driver and Device Tree
Tegra BSP supports a variety of modes on HDMI and DP monitors, including the CEA modes and detailed timing modes from the display EDID.
Setting HDMI or DP Screen Resolution
The screen resolution can be modified using xrandr utility or RandR protocol available at:
To change the default HDMI/DP screen resolution
1. Export the DISPLAY variable.
export DISPLAY=:0
2. Obtain the applicable resolutions list.
The resulting output shows a list of the HDMI, DP, or DSI display settings, if connected.
3. Switch the resolution to the desired display resolution.
xrandr --output HDMI-0 --mode <res>
xrandr --output DP-0 --mode <res>
Where <res> is the desired resolution, for example, 640x480.
The highest rate supported, for the specified mode, is automatically chosen.
4. Select the desired refresh rate.
xrandr --output HDKI-0 --moe <res> --rate <refresh_rate>
Where <refresh_rate> is the desired refresh rate, for example, 60.
Use xrandr to display all the supported refresh rates for a mode.
Mirroring or Extending Displays
When multiple displays are connected, you can choose the relative position of each monitor (HDMI or DP) or panel (DSI).
To choose the relative position of each monitor
1. Execute the following command to mirror the HDMI monitor with the DSI panel.
xrandr --output HDMI-0 --same-as DSI-0
2. Execute the following command to extend the display environment by placing the HDMI monitor to the left of the DSI panel.
xrandr --output HDMI-0 --left-of DSI-0
3. Execute this command to place the DP monitor to the right of the DSI panel.
xrandr --output DP-0 --right-of DSI-0
Determining Display Timing Values
Use this procedure to determine the timing values when referring to the LCD specification and the signal polarities as well as the constraints for picking the ref_to_sync values.
Display Controller Timing Diagram
The display controller timing for vertical and horizontal timing is as follows. Only the back porch can be a negative value, though it is typically positive.
Back porch—the distance between the trailing edge of the sync and the beginning of the active area. Some LCD specifications define the back porch from the leading edge of the sync rather than the trailing edge.
Front porch—the distance between the end of the active area and the leading edge of the sync.
Vertical timing—is in terms of lines.
Horizontal timing—is in terms of pixels.
Sync polarity—is in terms of the sync width; active low means the sync width pulse will be low, as in the diagram.
Pixel clock polarity—is in terms of when data will transition; an active low pixel clock means that the data changes on the falling edge of the clock, to be latched on the rising edge.
Data enable polarity (also called display enable or DE)—selects the level of the signal during the active area of display. The diagram has DE active high.
Configuring the Display Serial Interface
Use these procedures to configure the Display Serial Interface (DSI). Both the DSI driver and the DSI panel must be configured. DSI driver configuration is set through the device tree. Details about display device tree bindings is available at:
Configuring the DSI panel requires the panel specification from the vendor. You must use the correct display configuration file for your particular platform.
To configure the DSI driver
Locate and edit the appropriate display configuration file depending on your release at:
<top>/hardware/nvidia/platform/tegra/common/kernel-dts/ /panel-<panel_type>.dtsi
Where <panel_type> specifies the characteristics encoded for the panel, using the format:
For example, the file panel-p-wuxga-10-1.dtsi configures the following panel:
Filename: panel-p-wuxga-10-1.dtsi
brand = p = Panasonic
scrRes = wuxga = WUXGA 1920 x 1200
scrSize = 10-1 = 10.1 inches
The dsi_bindings structure encapsulates all the controller configuration options, specified in files at:
The naming format is:
Where <node_type> is dc, hdmi, dp, or dsi.
To configure the DSI panel
1. Configure the regulators.
The details depend on the board schematics.
2. Configure the General-Purpose Input/Outputs (GPIOs) required for resetting and backlighting the panel.
Some panels are more demanding and may require other GPIOs as well.
3. Set up the initialize/suspend sequence.
These are passed as device tree bindings in the power tree for the platform and read in the following file:
Jetson TX1:
Jetson TX2:
Configuring the Display Port
This topic describes how to enable the Display Port (DP), to map DP to a particular display controller (dc), and assign SOR bindings or enable dpaux appropriately.
The base device tree file is available at:
Enable the following nodes in this file:
host1x {
nvdisplay@15220000 {
status = “okay”;
nvidia,dc-or-node = "/host1x/sor";
sor {
status = “okay”;
dp-display {
status = “okay”;
dpaux@155c0000 {
status = “okay”;
Configuring Pulse Width Modulation
Backlight control to the panel is done through Pulse Width Modulation (PWM) or Parametric Four-Wave Mixing (PWFM) or through the backlight device embedded in the panel.
The PFW and PFWM driver located at:
The driver file for the backlight device embedded in the panel is:
For example, the backlight for the LG 5 inch 720p panel on pluto is driven by the embedded max8831 integrated circuit (IC). That driver file is:
To make backlight increment in a linear manner to the brightness increment, backlight is calibrated and the corresponding values are stored in the backlight response curve.
Hard-coding Kernel Display Boot Mode for HDMI
The Linux kernel boot logs and text-mode login prompt fails to display on some monitors due to a known fbconsole pixel clock calculation issue.
Affected monitors include:
Acer S277HK
Dell 24-inch 4K monitor
Viewsonic VP2780
Samsung 8500 UHD TV
NEC MultiSync LCD2070VX
LG Flatron W2246
NVIDIA has packaged a utility to update the kernel DTB file and workaround this issue.
To update the kernel DTB file
1. Navigate to the kernel directory at:
2. Execute this command to update the DTB:
./nv-enable-hard-coded-kernel-boot-display-mode.sh dtb/tegra186-quill-p3310-1000-c03-00-base.dtb
3. Flash the system.
Upon successful booting, the fbconsole displays in the specified mode. The default display mode is 720x480p@60Hz CEA.
The DTB file locations are available at:
To specify a different mode other than the default
1. Open the utility in your favorite editor.
2. In the properties array, update the values to the left of the : (colon) for each of the mode parameters.
3. Save the utility script and exit the editor.
4. Re-execute the utility by using the instructions to update the kernel DTB file.
Any known working mode on the given Monitor/TV can be specified instead of the 720x480p mode.
If the nvidia,fbcon-default-mode node already exists, the script may print an error message. It is safe to ignore this message.
By default, the HDMI is mapped to SOR1on both the platforms. If you updated it to SOR0, ensure that the node path is also updated and assigned to fbcon_node variable in the script.
Panel Driver and Device Tree
The source files and configuration files for the DSI panel driver and device tree examples are as follows.
Internal DSI panel driver and device tree examples
Device tree:
Appropriate nodes must be enabled in the device tree. The base device tree file is available at:
Enable the DC, DSI, and appropriate panel node.
Update the dc-or-node property to map DSI to a particular controller as follows:
host1x {
nvdisplay@15200000 {
status = “okay”;
nvidia,dc-or-node = "/host1x/dsi";
dsi {
status = “okay”;
panel-s-wuxga-8-0 {
status = “okay”;