NVIDIA Tegra Linux Driver Package

Development Guide
28.3 Release

Power Management for TX1 Devices
Interacting Features
Kernel-Space Power Saving Features
Chipset Power States
Clock and Voltage Management
Regulator Framework
CPU Power Management
Frequency Management with cpufreq
Idle Management with cpuidle
Memory Power Management
Thermal Management
Linux Thermal Framework
Thermal Zone
Configuring a Thermal Zone via the Device Tree
Thermal Sensing in Linux
NCT Sensors
Thermal Cooling
Fan Management
Clock Throttling
Software Thermal Shutdown
Software-based Power Consumption Modeling
Related Tools and Techniques
Disabling 3D Frequency Scaling
Setting Frequencies
Maximizing Tegra Performance
Using CPU Hot Plug
NVIDIA® Tegra® system-on-a-chip (SOC) and NVIDIA® Tegra® Board Support Package (BSP) provides many features related to power management, thermal management, and electrical management. These features deliver the best user experience possible given the constraints of a particular platform. The target user experience ensures the perception that the device provides:
Uniformly high performance
Excellent battery life
Perfect stability
Comfortable and cool to the touch
Interacting Features
Power, thermal, and electrical management features dynamically constrain knobs, such as:
Clock gate settings
Clock frequencies
Power gate (or regulator enable) settings
Processor power state (i.e., which idle state is selected for the CPU)
Peripheral power state (i.e., which idle state is selected for an I/O controller)
Chipset power state
Availability of CPU cores to the OS
Some of these knobs are constrained by more than one feature. For example, cpufreq implements load based scaling based on the how busy the CPU is and adjusts the CPU frequency accordingly. CPU thermal management, however, can override the target frequency of cpufreq. Consequently, before attempting to debug power, performance, thermal, or electrical problems, familiarize yourself with all of the power, thermal, and electrical management features present in the BSP.
Kernel-Space Power Saving Features
This section describes the features that Tegra implements several features to save power and extend battery life. Many of these features are implemented by the Linux kernel, with support from firmware and hardware, and without significant involvement from user-space.
Chipset Power States
The supported power states are listed in order of increasing flexibility or configurability:
Off: There is only one way for a system to be off.
SC7 minimally flexible Deep Sleep (SC7) offers a small amount of configurability. For example, prior to entering Deep Sleep, software can select which of the many hardware wake events are allowed to wake the chip from Deep Sleep.
Active state is extraordinarily flexible in terms of power and performance: It encompasses activity levels from low power audio playback through peak performance scenarios. Power consumption in the active state can range from tens of milliwatts up to multiple Watts.
Supported Power States
The supported power states are as follows:
Power State
Power rails
None of the power rails supplying Tegra and DRAM are powered.
No state is maintained in Tegra or DRAM.
The only way to exit this state is via a cold-boot (into active mode).
Deep Sleep (SC7)
Power rails
VDD_RTC, VDDIO_DDR, VDDIO_SYS, and DRAM power rails are powered on. VDD_CORE and VDD_CPU are powered off.
Tegra maintains a small amount of state in the PMC block. DRAM maintains state.
Exit from this state occurs based on a pre-defined set of wake events into active mode.
Power rails
VDD_RTC, VDDIO_DDR, VDDIO_SYS, VDD_CORE, and DRAM power rails are powered on. Other power rails (including VDD_CPU) may be on.
Software actively manages the power states of the many devices comprising Tegra.
Software can initiate a transition from Active to any other power state.
Power State Mapping to Linux
Tegra BSP maps these hardware power states onto Linux Power States as follows.
OS Power State
Chipset Power State
Software can choose whether to enter SC7 before the OS enters suspend.
Running/Idle (display on or off)
Many of the devices within Tegra may be idle or disabled. They are under driver control. For example, VDD_CPU may be powered off and the companion CPU may be power-gated.
NVIDIA Tegra X1 uses SCy instead of LPx for the name of the chipset power state.
Clock and Voltage Management
Because frequency is proportional to voltage, dynamic voltage scaling is closely related to frequency scaling. For example, higher frequencies require higher voltages and vice versa.
Most clock register manipulation on Tegra X1 is handled by Linux Kernel. The Linux kernel driver on the CPU exposes simplified view of the physical clock tree to software on the main CPU via the Linux Common Clock Framework.
Regulator Framework
The Linux regulator framework provides an abstraction that allows regulator consumer drivers to dynamically adjust voltage or current regulators at runtime, without knowledge of the underlying hardware power tree.
The framework provides a mechanism that platform initialization code can use to declare a power tree topology and assign a driver that provides regulators for each node in the hardware power tree. Such a driver is called a regulator provider driver.
Tegra BSP configures the platform power tree appropriately for Tegra devices. Additionally, drivers within Tegra BSP act as regulator consumers, where appropriate.
When porting Tegra BSP to a new platform, ensure that the platform power tree is configured correctly to match the underlying hardware. Additionally, ensure that all drivers for peripheral devices correctly make use of the regulator consumer APIs. BSP drivers registering as regulator consumers can cause I/O pads on the chip to be unavailable for other functions. Ensure that the Device Tree and board configuration file information for your new platform avoids conflicts between functions using the same I/O pads.
CPU Power Management
Tegra CPU power management strategy includes dynamic frequency scaling with dynamic voltage scaling, idle power states, and core management tuned for the Tegra X1 architecture.
Frequency Management with cpufreq
Tegra BSP implements CPU Dynamic Frequency Scaling (DFS) with the Linux cpufreq subsystem. The cpufreq subsystem comprises:
Platform drivers to implement the clock adjustment mechanism.
Governors to implement frequency scaling policies.
Core framework to connect governors to platform drivers.
The policy for frequency scaling depends on which cpufreq governor is selected at runtime.
For details consult the information available at:
For each Tegra hardware reference design, a cpufreq governor is selected and tuned to achieve a balance between power and performance.
When a governor requests a CPU frequency change, the Tegra-specific cpufreq platform driver reconciles that request with limits imposed by thermal or electrical limits. The driver updates the clock speed of the CPU.
Tegra X1 uses an DFLL to clock each CPU. Hardware (with the assistance of the Linux Kernel) ensures that the CPU voltage is appropriate for the DFLL to deliver requested CPU frequencies.
Idle Management with cpuidle
The Linux cpuidle infrastructure supports the implementation of SoC-specific idle states for each CPU core. cpuidle lacks direct support for idle states applicable to an entire CPU cluster and for idle states extending beyond a CPU cluster.
For more information on the Linux cpuidle infrastructure, see:
NVIDIA provides a Tegra-specific cpuidle driver that plugs into the cpuidle framework to enable CPU idle power management.
Per-Core CPU Idle States
The Tegra cpuidle driver exposes two per-core CPU idle states as follows:
Core State
The CPU core is clock-gated.
Transition CPU Cluster to Idle
When the final core within a cluster transitions to idle, the Tegra-specific cpuidle driver can transition the CPU cluster to a cluster idle state.
Cluster State
The CPU cluster’s clock is halted.
Additionally, as the final core within a cluster transitions to idle, the Tegra cpuidle driver optionally disables any SoC resources where the CPU was the last active user.
For example, the final CPU core transitioning to idle can optionally do one or more of the following:
Transition DRAM to self-refresh
Clock-gate MC/EMC
Halt various PLLs
CPU Idle
The idle task is scheduled when there are no runnable tasks left in the runqueue for a particular core. This task, through the cpuidle driver and cpuidle governor, selects the core and puts it into a low-power state, where it stays until an interrupt wakes it up to process more work.
When the last active core in a CPU cluster goes into an idle or offline state, the idle task puts the entire CPU cluster in a low power-state.
CCPLEX Idle States
Core states are denoted Cx states, cluster states are denoted as CCx states, and CCPlex states are denoted as CCPx states. The table below summarizes the different states available on the T210.
Core states
Cluster states
Auto clock-gating
Non-cpu power-gating
Using KConfig and Device Tree Node to Enable cpuidle
Use KConfig and the Device Tree node to enable cpuidle.
To enable cpuidle from the configuration file
Set the following option:
To enable cpuidle from device tree
Use the following compatibility string if not already enabled:
cpuidle {
compatible = "nvidia,tegra210-cpuidle";
status = "okay";
To get and set a CPU’s core power state
On a CPU core, the pathnames of the nodes that represent core states are:
C7: /sys/devices/system/cpu/cpu<x>/cpuidle/state1/*
To get the status of a core power state on core <x>, read the appropriate node. To set the status, write an ASCII 0 or 1 to the node.
ASCII 1 corresponds to “disabled,” and 0 to “enabled.”
To get cluster states
To get the status of the cluster states that are enabled for A57 cluster, run following command:
cat /sys/kernel/debug/cpuidle_t210/fast_cluster_states_enable
The value returned is:
name idx Enabled
c7 1 1
cc6 2 1
cc7 3 1
sc2 4 1
sc3 5 1
sc4 6 1
To get the per-core state statistics
To get the number of times the kernel requested a specified core to enter a specified state, read the following node:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/usage
To get the total time in microseconds that a specified core has spent in a specified state since boot, read the following device:
cat /sys/devices/system/cpu/cpu<x>/cpuidle/state<y>/time
For example, to get the number of times that A57 core 2 has entered state CC6, run the following command:
cat /sys/devices/system/cpu/cpu2/cpuidle/state2/usage
To get the total time in microseconds that A57 core 2 has spent in state CC6, run the following command:
cat /sys/devices/system/cpu/cpu2/cpuidle/state2/time
To disable cpuidle at boot time
Remove or disable the compatibility string nvidia,tegra210-cpuidle from the appropriate device tree file.
To disable a core/cluster power state at boot time
Remove or disable the appropriate core/cluster state nodes from the following device trees:
Memory Power Management
Tegra chipsets include power saving features whose operation is largely invisible to software at runtime. Most of those features are statically enabled at boot, according to settings in the boot configuration table (BCT).
Additionally, Tegra BSP implements EMC frequency scaling, which is dynamic frequency scaling for the memory controller (EMC/MC) and DRAM. This is a critical power saving feature that requires tuning and characterization for each new printed circuit board design.
The calibration results include a BCT and an EMC DVFS table specific to the board design. The EMC DVFS table must be included in the platform kernel device tree file.
EMC Frequency Scaling Policy
The following factors affect EMC frequency scaling policy at runtime:
The entries in the EMC DVFS table
The average memory bandwidth being used (as measured by hardware)
Requests made by various device drivers (cpufreq, graphics drivers, USB, HDMI™, and display)
Any limits dynamically imposed by thermal throttling
Thermal Management
Thermal Management is essential for system stability and quality of user experience. The Tegra X1 thermal management provides the following capabilities:
Sensing: for temperature reporting
Cooldown: for removing heat via the fan and for controlling heat via the software clock throttling
Slowdown: for hardware clock throttling
Shutdown for orderly software shutdown and hardware thermal reset
Tegra X1 thermal management is performed by the software on the main CPU.
The following table identifies each thermal management action and the associated module for the Tegra chip.
Thermal Action
Module Name
Tegra X1
Kernel software
Kernel software
Kernel software
Cooldown for software throttling
Kernel software
Kernel software
Slowdown for hardware throttling
Kernel software
Software shutdown
Kernel software
Hardware shutdown
soctherm.c and aotag.c
Kernel software
Linux Thermal Framework
The Linux thermal framework provides generic user-space and kernel-space interfaces for working with devices that measure temperature and devices used to control temperatures. The central component of the framework is the Thermal Zone.
More information about the Linux thermal framework is available at:
Thermal Zone
A thermal zone is a virtual object that represents an area on the die whose temperature is monitored and controlled. Essentially, a working thermal zone is more than a sensor, but acts as an object with the following components:
Temperature sensor
Cooling device
Trip points
Tegra BSP includes drivers that provide interfaces defined by these components.
This topic introduces these components and demonstrates how they form a thermal zone on a Tegra-based device.
Configuring a Thermal Zone via the Device Tree
The thermal zone provides knobs to tune the thermal response of the zone. Tegra BSP provides several thermal zones tuned to provide optimum thermal performance. These provided thermal zones can be modified by editing the entries in the device tree. Users can define sensors to use temperature limits and cooling actions on those limits. When a device becomes too hot, in most cases, it can be resolved by tuning the thermal zone.
The following code snippet provides an example of a thermal zone for the TX1 platform. This thermal zone monitors the temperature of the THERMAL_ZONE_CPU sensor. The clock throttling is performed using the CPU-balanced cooling device when the passive trip point, cpu_throttle, is crossed at 97 degrees Celsius.
CPU-therm {
thermal-zone-params {
governor-name = "step_wise";
trips {
cpu_critical {
temperature = <102000>;
hysteresis = <0>;
type = "critical";
cpu_heavy {
temperature = <100500>;
hysteresis = <0>;
type = "hot";
cpu_throttle {
temperature = <97000>;
hysteresis = <0>;
type = "passive";
cooling-maps {
map0 {
trip = <&{/thermal-zones/CPU-therm/trips/cpu_critical}>;
cdev-type = "tegra-shutdown";
cooling-device = <&{/soctherm@0x700E2000/throttle@critical}
map1 {
trip = <&{/thermal-zones/CPU-therm/trips/cpu_heavy}>;
cdev-type = "tegra-heavy";
cooling-device = <&throttle_heavy 1 1>;
map2 {
trip = <&{/thermal-zones/CPU-therm/trips/cpu_throttle}>;
cdev-type = "cpu-balanced";
cooling-device = <&{/bthrot_cdev/cpu_balanced}
More information about thermal knobs is available at:
Temperature Sensors
A temperature sensor in a thermal zone is responsible for reporting the temperature in milli-Celsius. Tegra has several types of temperature sensors spread across on the die and board.
For more information see Thermal Sensing in Linux.
Trip Points
Trip points are used to communicate with the thermal zone. The trip point identifies the temperature at which to perform a thermal action. Trip points are classified as active or passive, based on the type of cooling they trigger. A trip point is classified as critical if it triggers a thermal shutdown. A cooling map specifies how a cooling device is associated with certain trip points. Tegra BSP supports fan and clock throttling.
Cooling Devices
A cooling device does not actually remove any actual heat; only fan cooling device can remove heat. The Linux thermal framework makes this distinction by classifying fan cooling as an “active” cooling device. Clock throttling, which is the other type of cooling device, is classified as a “passive” cooling device.
For more information see Fan Management and Clock Throttling.
Thermal management requires some form of feedback control system that keeps the device within a safe operating temperature. The governor implements this feedback control loop. While the Linux thermal framework provides many different governors, Tegra BSP provides a simple Proportional Integral Derivative (PID) controller for all passive throttling needs.
Tegra BSP Specific Thermal Zones
Platform specific thermal zones are provided in the Tegra BSP. They are tuned to provide the best performance within the thermal constraints of the device. Each thermal zone uses a temperature sensor that is controlled by Linux kernel as described in the following table.
Thermal Zone
Thermal Sensor
ABI Name
Cooling Action
Balanced Throttle Temperature in Degrees Celsius
All gains achieved by tuning are limited by the Thermal Design Power (TDP) of the system. Tuning cannot remedy a faulty TDP, and removing all the thermal zones does not guarantee maximum performance because it can cause irreversible damage to the device and/or resets.
Thermal Sensing in Linux
The Tegra platform includes several drivers for temperature sensing.
NCT Sensors
Tegra BSP includes a driver for devices such as:
These devices can sense their own temperature as well as sensing the temperature of a remote diode. Tegra platforms have these sensors setup as follows:
Thermal Zone
Thermal Sensor
Sensed Location
Remote sensor
Temperature on die near GPU
Local sensor
Temperature of the board
Tegra BSP configures this sensor to operate in an extended mode to increase the temperature range to 64 Degrees Celsius to 191 degrees Celsius.
Operation During SC7
On many platforms, the voltage rail that powers the sensor is gated when Tegra enters SC7 state. Consequently, the sensor is stopped when Tegra enters SC7 and turned back on when Tegra exits SC7 state.
Thermal Capabilities
The NCT sensors generate thermal events for:
Thermal zone trip points
Hardware thermal shutdown
Correction Offset
The NCT sensors allow software to program a static offset temperature for the remote sensor. This accounts for any inaccuracy that may be present in the sensor hardware. Tegra BSP reads the offset from the Device Tree and programs into the offset register on boot. The offset is calculated and validated via oil bath experiments.
Thermal Cooling
Tegra BSP provides thermal management using fan control and throttling of various clocks in the system.
Fan Management
Fan management in Tegra BSP is provided using active cooling in the form of fan control. The cooling device pwm-fan provides:
Fan speed control by programming the PWM controller
Ramp-up and ramp-down control to change the speed of the fan smoothly
Fan control during various power states
The PWM-RPM mapping, and the various ramp rates, are stored as part of the device tree binary. The pwm-fan cooling device maps these PWM values to a cooling state. The fan cooling device can be attached to monitor the temperature of any of the Tegra BSP sensors. As the temperature increases, the governor progressively picks a deeper cooling state for the fan. This results in a higher RPM for the fan which then results in more cooling.
Tegra thermal management uses the fan as the first line of defense to delay clock throttling until a much higher temperature.
Clock Throttling
Tegra BSP provides thermal cooling by throttling various clocks in the system. When a rising temperature crosses a trip point, clock throttling relies on the DVFS capabilities of the clocks to reduce their operating frequency, and thereby the voltage of the rail that powers the clock. This lowered frequency and voltage reduces the power consumption which then helps in controlling the temperature.
Because cooling is achieved by reducing the clock frequency, there is a direct impact on the performance and user experience. If a device feels warm and seems sluggish, it may be due to thermal throttling on the clocks. This can be remedied by tuning the thermal zone provided in the following Tegra BSP balanced cooling devices:
Each of these balanced cooling devices provides several cooling states that translate to a maximum allowable operating frequency for the CPU, GPU, and EMC clocks. These frequencies are optimized to provide the best possible performance at a given temperature. The frequency tables for these clocks are part of the device tree binary.
The governor uses the current temperature of the sensor as an input to the feedback control loop. Similarly, the governor uses the output is as the new cooling state for the operation of the cooling device. As the device heats up, the governor progressively picks a higher cooling which then results in a higher frequency cap for all the clocks, and potentially higher cooling. Tegra BSP performs this thermal throttling of the clocks to maintain the junction temperature of the die within the recommended safe limits.
Software Thermal Shutdown
The thermal zones also define a special type of trip point called a critical trip point that triggers a software shutdown. This special trip point allows the operating system to save its state and perform an orderly shutdown before a hardware reset due to high temperature rates. Tegra BSP defines one critical trip point per thermal zone. Users can set the lower limit for the orderly shutdown. A thermal shutdown occurs after all the other cooling strategies have failed. It is considered a rare event. The shutdown limits are as follows.
Thermal Zone
Shutdown Limit in Degrees Celsius
Software-based Power Consumption Modeling
The Jetson TX1 module has 3-channel INA3221 power monitor at I2C address 0x40.
The information from the INA3221 power monitor can be read using sysfs nodes. The naming convention for sysfs nodes is as follows:
Exports the rail name.
Exports rail current in mA.
Exports rail voltage in mV.
Exports rail power in mW.
Where <N> is a channel number 0-2.
The INA driver may also present other nodes. Do not modify any INA sysfs node value. Modifying these values can result in damage to your device.
The sysfs nodes to read for rail names, voltage, current, and power are at:
The rail names for I2C address 0x40 are:
Rail Name
Channel 0: VDD_IN
Main module power input.
Channel 1: VDD_GPU
GPU power rail.
Channel 2: VDD_CPU
CPU power rail.
The Jetson TX1 Developer Kit carrier board has 3-channel INA3221 power monitors at I2C addresses 0x42 and 0x43. The sysfs nodes to read rail name, voltage, current and power are at:
The rail names for I2C address 0x42 are:
Rail Name
Channel 0: VDD_MUX
Carrier board power input.
Channel 1: VDD_5V_IO_SYS
Carrier board 5 V supply.
Channel 2: VDD_3V3_SYS
Carrier board 3.3 V supply.
The rail names for I2C address 0x43 are:
Rail Name
Channel 0: VDD_3V3_IO_SLP
Carrier board 3.3 V sleep supply.
Channel 1: VDD_1V8_IO (Name on schematic is VDD_1V8)
Carrier board 1.8 V supply.
Channel 2: VDD_3V3_SYS_M2
3.3 V supply for M.2 Key E connector.
To read INA3221 at 0x40, the channel-0 rail name (i.e., VDD_IN), execute the command:
cat /sys/bus/i2c/drivers/ina3221x/1-0040/iio:device1/rail_name_0
To read VDD_IN voltage, current, and power, execute the commands:
cat /sys/bus/i2c/drivers/ina3221x/1-0040/iio:device1/in_current0_input
cat /sys/bus/i2c/drivers/ina3221x/1-0040/iio:device1/in_voltage0_input
cat /sys/bus/i2c/drivers/ina3221x/1-0040/iio:device1/in_power0_input
In terms of accuracy, assume a 5% guard band for INA measurements greater than 200 mW. Below that, accuracy can deviate by as much as 15%.
Related Tools and Techniques
The tools and techniques to manage power are as follows.
Disabling 3D Frequency Scaling
3D frequency scaling is enabled by default.
To disable 3D frequency scaling
Run the following command:
echo 0 > /sys/devices/57000000.gpu/enable_3d_scaling
To enable 3D frequency scaling
Run the following command:
echo 1 > /sys/devices/57000000.gpu/enable_3d_scaling
Setting Frequencies
To get system clock information
Run the following command:
cat /sys/kernel/debug/clk/clk_summary
To print the CPU lower bound, upper bound, and current frequency
Run the following commands:
cat /sys/devices/system/cpu/cpuX/cpufreq/cpuinfo_min_freq
cat /sys/devices/system/cpu/cpuX/cpufreq/cpuinfo_max_freq
cat /sys/devices/system/cpu/cpuX/cpufreq/cpuinfo_cur_freq
To change the CPU upper bound
Run the following command:
echo <cpu_freq> > /sys/devices/system/cpu/cpuX/cpufreq/scaling_max_freq
To change the CPU lower bound
Run the following command:
echo <cpu_freq> > /sys/devices/system/cpu/cpuX/cpufreq/scaling_min_freq
To set the static CPU frequency
Run the following command:
echo <cpu_freq> > /sys/devices/system/cpu/cpuX/cpufreq/scaling_min_freq
echo <cpu_freq> > /sys/devices/system/cpu/cpuX/cpufreq/scaling_max_freq
<cpu_freq> is the frequency value available at:
<X> is the CPU core number.
To print the GPU lower bound, upper bound, and current frequency
Run the following commands:
cat /sys/devices/57000000.gpu/devfreq/57000000.gpu/min_freq
cat /sys/devices/57000000.gpu/devfreq/57000000.gpu/max_freq
cat /sys/devices/57000000.gpu/devfreq/57000000.gpu/cur_freq
To change the GPU upper bound
Run the following command:
echo <gpu_freq> > /sys/devices/57000000.gpu/devfreq/57000000.gpu/max_freq
To change the GPU lower bound
Run the following command:
echo <gpu_freq> > /sys/devices/57000000.gpu/devfreq/57000000.gpu/min_freq
To set the static GPU frequency
Run the following command:
echo <gpu_freq> > /sys/devices/57000000.gpu/devfreq/57000000.gpu/min_freq
echo <gpu_freq> > /sys/devices/57000000.gpu/devfreq/57000000.gpu/max_freq
Where <gpu_freq> is the value available in:
To print the EMC lower bound, upper bound, and current frequency
Run the following commands:
cat /sys/kernel/debug/tegra_bwmgr/emc_min_rate
cat /sys/kernel/debug/tegra_bwmgr/emc_max_rate
cat /sys/kernel/debug/tegra_bwmgr/emc_rate
To set static EMC frequency
Run the following commands:
echo <emc_freq> > /sys/kernel/debug/clk/override.emc/clk_update_rate
echo 1 > /sys/kernel/debug/clk/override.emc/clk_state
Where <emc_freq> is frequency value between emc_min_rate and emc_max_rate.
Maximizing Tegra Performance
Tegra BSP provides the jetson_clocks.sh script to maximize Jetson-TX1 performance by setting static maximum frequency to the CPU, GPU, and EMC clocks. Use the script to show current clock settings, store current clock settings into a file, and restore clock settings from a file.
The script is available at:
The command usage is as follows:
jetson-clocks.sh [options]
Displays the current settings.
--store [file]
Stores the current settings to a file.
The default file is l4t_dfs.conf.
--restore [file]
Restores the saved settings from the file.
The default file is l4t_dfs.conf.
To show the current settings
Execute the command:
sudo ${HOME}/jetson_clocks.sh --show
To store the current settings
Execute the command:
sudo ${HOME}/jetson_clocks.sh --store
To maximize Jetson TX1 performance
Execute the command:
sudo ${HOME}/jetson_clocks.sh
To restore the previous settings
Execute the command:
sudo ${HOME}/jetson_clocks.sh --restore
Using CPU Hot Plug
You can manage the CPU hotplug as follows.
To manually turn on/off slave CPUs
1. Run the following command to turn on the slave CPU:
echo 1 > /sys/devices/system/cpu/cpuX/online
2. Run the following command to turn the slave CPU off:
echo 0 > /sys/devices/system/cpu/cpuX/online
To check CPU state
Run the following command:
cat /sys/devices/system/cpu/cpuX/online
Where <X> is the CPU core number.