NVIDIA Jetson Linux Developer Guide
32.4.3 Release



Overriding Default Clock Rates
Configuring GPU Clocks
Configuring Clocks
NVIDIA® Jetson™ Board Support Package (BSP) supports configuring Jetson clocks and peripheral clocks through the software. This topic describes how to check clock status, get maximum rates for clocks, and configure clock sources.
For information about available Jetson clock sources and capabilities, see the “Clock and Reset Controller” section of the Technical Reference Manual (TRM) for your Jetson processor. This section of the TRM also describes clock source multiplexers and provides descriptions of available clock sources for each component.
In kernel 4.9 and following, the common clock framework (CCF) is supported. As a result:
All device drivers use the public CCF APIs include/linux/clk.h, and include/linux/clk-provider.h, including functions such as clk_get, clk_enable, devm_clk_get, clk_prepare_enable, clk_prepare_disable, clk_disable, and others, instead of platform-specific APIs.
All clock drivers, including the Jetson custom clk driver, implement clk_ops.
Clock sources and clocks required by devices are defined in the Device Tree.
Clocks are controlled by an R5 called the Boot and Power Management Processor. It runs RTOS software from bpmp.bin. The Linux kernel running on CCPLEX requests this software for clock programming.
The NVIDIA® Jetson™ Linux Driver Package (L4T) clock driver wrapper is available in the nvidia/drivers/clk/tegra/ directory.
To check clock status
Applies to: Jetson AGX Xavier series and Jetson TX2 series
On the device, enter the following command to launch debugfs and check the clock:
sudo -s
# cat /sys/kernel/debug/bpmp/debug/clk/clk_tree
This is an example of debugfs output for NVIDIA® Jetson AGX Xavier™ series:
A screenshot of a cell phone Description generated with very high confidence

Overriding Default Clock Rates

The default clock rate of each component is set during boot and updated under control of the driver by requesting BPMP. The debugfs service provides a way to override the default clock rate and set a fixed clock rate. Use debugfs for debugging and experimental purposes only.
You can find the child nodes shown below under each clock node. You can use them to change the nodes’ parent and rates. For example:
root@jetson-0422818069479:/sys/kernel/debug/bpmp/debug/clk/can1# ls
all children children dvfs
flags fmon hz _ off
max_rate min_rate mrq_rate_locked parent
possible_parents pto_counter rate state
The Jetson AGX Xavier clocks are controlled by BPMP. For example, override the EMC rate with the following commands:
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/mrq_rate_locked
echo 1 > /sys/kernel/debug/bpmp/debug/clk/emc/state
echo x > /sys/kernel/debug/bpmp/debug/clk/emc/rate

Configuring GPU Clocks

With GPU DVFS enabled using the devfreq framework, GPU frequency changes based on load. You can instead run the GPU at a fixed frequency if necessary.
To run the GPU at a fixed frequency
1. Enter the following command.
For gp10b:
# cd /sys/devices/17000000.gp10b/devfreq/17000000.gp10b/
For gv11b:
# cd /sys/devices/gpu.0/devfreq/17000000.gv11b/
2. List the available frequencies:
cat available_frequencies
114750000 216750000 318750000 420750000 522750000 624750000 675750000 828750000 905250000 1032750000 1198500000 1236750000 1338750000 1377000000
3. Fix the frequency.
To fix the frequency at maximum supported frequency:
echo <max> min_freq
Where <max> in the maximum supported frequency. For example, to fix the frequency at the maximum supported frequency from the list in step 2:
echo 1377000000> min_freq
To fix any other supported frequency:
echo <freq> > min_freq
echo <freq> > max_freq
Where <freq> in the desired supported frequency. For example, to fix the frequency at 828750000:
echo 828750000 > min_freq
echo 828750000 > max_freq

Configuring Clocks

In general, each block or module has a dedicated clock source register. For detailed information about a given register, see CLK_RST_CONTROLLER_CLK_SOURCE_<module_name> in the Technical Reference Manual (TRM).
Clock source registers provide clock source selection and clock divider control for the module. The divider is typically 8 bits, 7 integer bits and 1 fractional bit (U7.1).
To change clock configurations in the kernel device driver module
1. Declare clocks in Device Tree. For example, for padctl-uphy, clocks can be declared as follows:
clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>,
<&tegra_car TEGRA210_CLK_USB2_TRK>,
<&tegra_car TEGRA210_CLK_PLL_E>;
clock-names = "hsic_trk", "usb2_trk", "pll_e";
2. Use the devm_clk_get function to obtain the desired clock source using clock-names.
3. Use the clk_get_parent function to obtain the parent clock for the desired clock.
4. Use the clk_set_parent function to select the specified clock source for the target clock.
5. Use the clk_set_rate function to set the frequency of the target clock.
The divider is calculated automatically according to the target rate. Successful clock frequency settings must meet the available divider of that module and the frequency of the clock source.
6. Use the clk_round_rate function to get the exact clock frequency that can be configured from the current clock source.
7. Use clk_prepare_enable (or clk_prepare and clk_enable) functions to ungate/enable the clock. The clk_prepare function can be used instead of clk_enable to ungate a clock if the operation may sleep.
To use PLLAON as clock source
Applies to: Jetson Xavier NX and Jetson AGX Xavier only
By default, PLLAON is disabled on T194 L4T platforms to conserve power.
You may want to enable PLLAON to achieve a higher clock rate or more accuracy in certain use cases like CAN and PWM. You can do this by first adding PLLAON as a possible parent of a clock, then setting the parent of the clock to PLLAON.
You make these changes by modifying the BPMPFW DTB and kernel DTB files. The BPMPFW DTB holds the configuration for clocks; the kernel DTB contains the setting that enables and disables PLLAON.
Taking the CAN use case as an example, follow these steps to add PLLAON as a possible parent:
1. Convert the BPMPFW DTB (e.g. tegra194-a02-bpmp-p2888-a04.dtb) to a DTS using the dtc tool.
2. Edit the DTS file to add the PLLAON clock ID to the list of possible parents.
You can obtain the clock ID for PLLAON from the header file tegra194-clock.h. In this example the clock ID is 94:
In the DTS file under clocks, add the clock ID to the allowed-parents list:
clocks {
clock@can1 {
clk-id = <9>; /* confirming TEGRA194_CLK_CAN1*/
allowed-parents <nn,nn,nn,...,94>; /*TEGRA194_CLK_PLLAON*/
This allows PLLAON to be set as parent of CAN1.
3. Convert the DTS file back to DTB.
4. Convert the kernel DTB (e.g, tegra194-p2888-0001-p2822-0000.dtb) to a DTS file using the dtc tool, or obtain the kernel’s source DTS file.
5. Edit the kernel DTS file to make CAN use PLLAON as parent and remove PLLAON from list of clocks to be disabled:
compatible = "nvidia,clocks-config";
disable {
/* Edit clocks property to remove clock provider + clock id pair for PLLAON. */
6. Change the mttcan node to select PLLAON as parent:
mttcan@c310000 {
pll_source = "pllaon";
clocks = <...>,
<&bpmp_clks TEGRA194_CLK_PLLAON>; /*New entry*/
clock-names = <name>, <name>, <name>, ..., "pllaon";
7. Convert the DTS file to DTB, or build the kernel DTB if you edited the source files.
8. Flash the board with the modified DTB files.
Clocks that Can Have PLLAON as Parent
The following clocks can be configured to have PLLAON as a parent: