9.2/sources/libs/gst-nvdstensor/nvdstensor.h

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/*
 * SPDX-FileCopyrightText: Copyright (c) 2020-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
#ifndef NVDSTENSOR_H_
#define NVDSTENSOR_H_
 
#include <stdint.h>
#include <stdbool.h>
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#define STRUCTURE_PADDING  4
 
typedef enum
{
  NVDSTENSOR_MAP_READ,       
  NVDSTENSOR_MAP_WRITE,      
  NVDSTENSOR_MAP_READ_WRITE, 
} NvDsTensorMemMapFlags;
 
typedef enum
{
  NVDSTENSOR_NCHW,
} NvDsTensorFormat;
 
typedef enum
{
  NVDSTENSOR_MEM_DEFAULT,
  NVDSTENSOR_MEM_CUDA_PINNED,
  NVDSTENSOR_MEM_CUDA_DEVICE,
  NVDSTENSOR_MEM_CUDA_UNIFIED,
  NVDSTENSOR_MEM_SYSTEM,
} NvDsTensorMemType;
 
typedef enum
{
  NVDSTENSOR_FP32,
  NVDSTENSOR_FP16,
  NVDSTENSOR_INT32,
  NVDSTENSOR_INT16,
  NVDSTENSOR_INT8
} NvDsTensorPrecision;
 
typedef struct NvDsTensorCreateParams {
  uint32_t gpuId;
 
  uint32_t n;
  uint32_t c;
  uint32_t h;
  uint32_t w;
 
  uint32_t size;
 
  bool isContiguous;
 
  NvDsTensorMemType memType;
  NvDsTensorFormat format;
  NvDsTensorPrecision precision;
 
} NvDsTensorCreateParams;
 
typedef struct NvDsTensor {
  uint32_t n;
  uint32_t c;
  uint32_t w;
  uint32_t h;
 
  void * dataPtr;
  void * mappedAddr;
 
  uint32_t dataSize;
 
  void * _reserved[STRUCTURE_PADDING];
} NvDsTensor;
 
typedef struct NvDsTensorArray {
  uint32_t gpuId;
 
  bool isContiguous;
 
  NvDsTensorMemType memType;
  NvDsTensorPrecision precision;
  NvDsTensorFormat format;
 
  uint32_t arraySize;
  uint32_t numFilled;
  NvDsTensor *tensorArray;
 
  void * _reserved[STRUCTURE_PADDING];
} NvDsTensorArray;
 
int NvDsTensorCreate (NvDsTensorArray **tensor, uint32_t arraySize,
                                NvDsTensorCreateParams *params);
 
int NvDsTensorDestroy (NvDsTensorArray *tensor);
 
int NvDsTensorMap (NvDsTensorArray *tensors, int index, NvDsTensorMemMapFlags type);
 
int NvDsTensorUnMap (NvDsTensorArray *tensors, int index);
 
#ifdef __cplusplus
}
#endif
#endif /* NVDSTENSOR_H_ */