NVIDIA DeepStream SDK API Reference
6.4 Release
deepstream_segvisual.h
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVGSTDS_SEGVISUAL_H__
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#define __NVGSTDS_SEGVISUAL_H__
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#include <gst/gst.h>
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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typedef
struct
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{
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GstElement *
bin
;
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GstElement *
queue
;
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GstElement *
nvvidconv
;
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GstElement *
conv_queue
;
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GstElement *
cap_filter
;
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GstElement *
nvsegvisual
;
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}
NvDsSegVisualBin
;
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typedef
struct
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{
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gboolean
enable
;
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guint
gpu_id
;
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guint
max_batch_size
;
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guint
width
;
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guint
height
;
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guint
nvbuf_memory_type
;
/* For nvvidconv */
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}
NvDsSegVisualConfig
;
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gboolean
create_segvisual_bin
(
NvDsSegVisualConfig
*config,
NvDsSegVisualBin
*bin);
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#ifdef __cplusplus
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}
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#endif
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#endif
NvDsSegVisualBin
Definition:
deepstream_segvisual.h:34
NvDsSegVisualConfig::gpu_id
guint gpu_id
Definition:
deepstream_segvisual.h:47
NvDsSegVisualConfig::width
guint width
Definition:
deepstream_segvisual.h:49
NvDsSegVisualBin::queue
GstElement * queue
Definition:
deepstream_segvisual.h:37
create_segvisual_bin
gboolean create_segvisual_bin(NvDsSegVisualConfig *config, NvDsSegVisualBin *bin)
Initialize NvDsSegVisualBin.
NvDsSegVisualBin::nvsegvisual
GstElement * nvsegvisual
Definition:
deepstream_segvisual.h:41
NvDsSegVisualBin::conv_queue
GstElement * conv_queue
Definition:
deepstream_segvisual.h:39
NvDsSegVisualConfig::max_batch_size
guint max_batch_size
Definition:
deepstream_segvisual.h:48
NvDsSegVisualConfig
Definition:
deepstream_segvisual.h:44
NvDsSegVisualBin::cap_filter
GstElement * cap_filter
Definition:
deepstream_segvisual.h:40
NvDsSegVisualBin::bin
GstElement * bin
Definition:
deepstream_segvisual.h:36
NvDsSegVisualConfig::enable
gboolean enable
Definition:
deepstream_segvisual.h:46
NvDsSegVisualConfig::nvbuf_memory_type
guint nvbuf_memory_type
Definition:
deepstream_segvisual.h:51
NvDsSegVisualConfig::height
guint height
Definition:
deepstream_segvisual.h:50
NvDsSegVisualBin::nvvidconv
GstElement * nvvidconv
Definition:
deepstream_segvisual.h:38
Advance Information | Subject to Change | Generated by NVIDIA | Mon Dec 11 2023 17:51:24 | PR-09318-R32