NVIDIA DeepStream SDK API Reference
6.4 Release
deepstream_tiled_display.h
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/*
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* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVGSTDS_TILED_DISPLAY_H__
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#define __NVGSTDS_TILED_DISPLAY_H__
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#include <gst/gst.h>
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#include "
nvll_osd_struct.h
"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
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typedef
struct
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{
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GstElement *
bin
;
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GstElement *
queue
;
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GstElement *
tiler
;
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}
NvDsTiledDisplayBin
;
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typedef
enum
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{
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NV_DS_TILED_DISPLAY_DISABLE
= 0,
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NV_DS_TILED_DISPLAY_ENABLE
= 1,
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NV_DS_TILED_DISPLAY_ENABLE_WITH_PARALLEL_DEMUX
= 2
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}
NvDsTiledDisplayEnable
;
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typedef
struct
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{
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NvDsTiledDisplayEnable
enable
;
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guint
rows
;
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guint
columns
;
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guint
width
;
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guint
height
;
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guint
gpu_id
;
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guint
nvbuf_memory_type
;
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guint
compute_hw
;
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guint
buffer_pool_size
;
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}
NvDsTiledDisplayConfig
;
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gboolean
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create_tiled_display_bin
(
NvDsTiledDisplayConfig
* config,
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NvDsTiledDisplayBin
* bin);
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#ifdef __cplusplus
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}
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#endif
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#endif
NvDsTiledDisplayEnable
NvDsTiledDisplayEnable
Definition:
deepstream_tiled_display.h:41
NvDsTiledDisplayConfig::rows
guint rows
Definition:
deepstream_tiled_display.h:57
NV_DS_TILED_DISPLAY_ENABLE_WITH_PARALLEL_DEMUX
@ NV_DS_TILED_DISPLAY_ENABLE_WITH_PARALLEL_DEMUX
When user sets tiler group enable=2, all sinks with the key: link-only-to-demux=1 shall be linked to ...
Definition:
deepstream_tiled_display.h:51
NvDsTiledDisplayConfig::width
guint width
Definition:
deepstream_tiled_display.h:59
create_tiled_display_bin
gboolean create_tiled_display_bin(NvDsTiledDisplayConfig *config, NvDsTiledDisplayBin *bin)
Initialize NvDsTiledDisplayBin.
NvDsTiledDisplayBin
Definition:
deepstream_tiled_display.h:34
NvDsTiledDisplayBin::bin
GstElement * bin
Definition:
deepstream_tiled_display.h:36
NvDsTiledDisplayConfig
Definition:
deepstream_tiled_display.h:54
NvDsTiledDisplayConfig::enable
NvDsTiledDisplayEnable enable
Definition:
deepstream_tiled_display.h:56
NvDsTiledDisplayBin::queue
GstElement * queue
Definition:
deepstream_tiled_display.h:37
NvDsTiledDisplayConfig::nvbuf_memory_type
guint nvbuf_memory_type
Definition:
deepstream_tiled_display.h:62
NvDsTiledDisplayBin::tiler
GstElement * tiler
Definition:
deepstream_tiled_display.h:38
NV_DS_TILED_DISPLAY_DISABLE
@ NV_DS_TILED_DISPLAY_DISABLE
Definition:
deepstream_tiled_display.h:43
NvDsTiledDisplayConfig::height
guint height
Definition:
deepstream_tiled_display.h:60
NvDsTiledDisplayConfig::gpu_id
guint gpu_id
Definition:
deepstream_tiled_display.h:61
nvll_osd_struct.h
NvDsTiledDisplayConfig::compute_hw
guint compute_hw
Compute Scaling HW to use Applicable only for Jetson; x86 uses GPU by default (0): Default - Default,...
Definition:
deepstream_tiled_display.h:69
NvDsTiledDisplayConfig::columns
guint columns
Definition:
deepstream_tiled_display.h:58
NV_DS_TILED_DISPLAY_ENABLE
@ NV_DS_TILED_DISPLAY_ENABLE
Definition:
deepstream_tiled_display.h:44
NvDsTiledDisplayConfig::buffer_pool_size
guint buffer_pool_size
Definition:
deepstream_tiled_display.h:70
Advance Information | Subject to Change | Generated by NVIDIA | Mon Dec 11 2023 17:51:24 | PR-09318-R32