NVIDIA Firmware Tools (MFT) Documentation v4.24.0
v4.24.0

mlxreg Utility

The mlxreg utility allows users to obtain information regarding supported access registers, such as their fields and attributes. It also allows getting access to register data from firmware and setting access register data on firmware.

Registers can be get/set in unknown (RAW) mode by providing register ID and length.

Note

Unknown (RAW) mode is risky as no checks are performed, please consult with Support before using it.

mst driver must be started prior to running mlxreg tool.

Some access registers depend on setup configuration such as link up/down. Invalid setup may cause failures.

To run mlxreg, use the following line:

Copy
Copied!
            

mlxreg [options]

where:

-h |--help

Displays help message.

-v |--version

Displays version info.

-d |--device <device>

Performs operation for a specified mst device.

-a |--adb_file <adb_file>

An external ADB file

--reg_name <reg_name>

Known access register name

--reg_id <reg_ID>

Access register ID

--reg_len <reg_length>

Access register layout length (bytes)

-i |--indexes <idxs_vals>

Register indexes

-g |--get

Register access GET

-s |--set <reg_dataStr>

Register access SET

--show_reg <reg_name>

Prints the fields of a given reg access (must have reg_name)

--show_regs

Prints all available access registers

--yes

Non-interactive mode, answer yes to all questions

Examples:

Show all available access registers (the example below shows a sample of the whole list):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --show_regs Available Access Registers ======================================================================================== CWTP CWTPM MCIA MLCR MPCNT MPEIN NCFG PAOS PDDR PMDR PMLP PPAOS PPCNT PPLM PPLR PPRT PPTT PTAS PTYS ROCE_ACCL SBCM SBDCR SBPM SBPR SBSR SLRG SLRP SLTP ......

Query a single access register (PAOS):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --show_reg PAOS Field Name | Address (Bytes) | Offset (Bits) | Size (Bits) | Access ========================================================================= oper_status | 0x00000000 | 0 | 4 | RO admin_status | 0x00000000 | 8 | 4 | RW local_port | 0x00000000 | 16 | 8 | INDEX swid | 0x00000000 | 24 | 8 | INDEX e | 0x00000004 | 0 | 2 | RW ee | 0x00000004 | 30 | 1 | WO ase | 0x00000004 | 31 | 1 | WO =========================================================================

Note: There might be indexes in access register fields that must be provided when setting or getting data.

Get access register data (PAOS with indexes: local port 1, swid 0):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --reg_name PAOS --get --indexes "local_port=0x1,swid=0x0" Field Name | Data ============================= oper_status | 0x00000001 admin_status | 0x00000001 local_port | 0x00000001 swid | 0x00000000 e | 0x00000000 ee | 0x00000000 ase | 0x00000000 =============================

Set access register data (PAOS with indexes: local_port 1 swid 0x0 and data: e 1):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --reg_name PAOS --indexes "local_port=0x1,swid=0x0" --yes --set "e=0x1" You are about to send access register: PAOS with the following data: Field Name | Data ============================= oper_status | 0x00000002 admin_status | 0x00000001 local_port | 0x00000001 swid | 0x00000000 e | 0x00000001 ee | 0x00000000 ase | 0x00000000 ============================= Do you want to continue ? (y/n) [n] : y Sending access register...

Get access register data (PAOS (0x5006) in unknown mode (RAW) with indexes: local_port=0x1 swid=0x0):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --reg_id 0x5006 --reg_len 0x10 --indexes "0x0.16:8=0x1,0x0.24:8=0x0" --get Address | Data ======================= 0x00000000 | 0x00010101 0x00000004 | 0x00000000 0x00000008 | 0x00000000 0x0000000c | 0x00000000 =======================

Set access register data (PAOS in unknown mode (RAW) with indexes: local_port=0x1 swid=0x0 and data e 1):

Copy
Copied!
            

mlxreg -d /dev/mst/mt4115_pciconf0 --reg_id 0x5006 --reg_len 0x10 --indexes "0x0.16:8=0x1,0x0.24:8=0x0" --yes --set "0x4.0:2=0x1" You are about to send access register id: 0x5006 with the following data: Address | Data ======================= 0x00000000 | 0x00010102 0x00000004 | 0x00000001 0x00000008 | 0x00000000 0x0000000c | 0x00000000 ======================= Do you want to continue ? (y/n) [n] : y Sending access register...

© Copyright 2024, NVIDIA. Last updated on Aug 26, 2024.