NVSHMEM Release 2.4.0

This is the NVIDIA® NVSHMEM™ 2.4.0 release notes.

Key Features And Enhancements

This NVSHMEM release includes the following key features and enhancements:

  • NVSHMEM can now be built without ibrc support by setting NVSHMEM_IBRC_SUPPORT=0 in the environment before building.

    This allows users to build and run NVSHMEM without the GDRCopy and OFED dependencies.

  • Added support for CUDA Multi-Process Service (MPS)​ that enables processes to share a GPU​.

  • Added limited support for Multiple-processes per GPU (MPG) without MPS​.

  • Added a local buffer registration API​.

  • Added support for dynamic symmetric heap allocation​, which eliminates the need to specify NVSHMEM_SYMMETRIC_SIZE​.

  • Removed redundant barriers to improve the collectives' performance​.

  • Support for large RMA messages​.

  • Support for calling nvshmem_init/finalizing multiple times with MPI bootstrap​.

  • Improved testing coverage (large messages, exercising full GPU memory, and so on)

  • Improved the default PE to a NIC assignment​.

  • Optimized channel request processing by CPU proxy thread​.

  • Added support for the shmem_global_exit API.

Compatibility

NVSHMEM 2.4.0 has been tested with the following:

Limitations

Systems with PCIe peer-to-peer communication require one of the following:
  • InfiniBand to support NVSHMEM atomics APIs.
  • The use of NVSHMEM’s UCX transport that, if IB is absent, will use sockets for atomics.

Fixed Issues

There are no fixed issues in this release.

Breaking Changes

There are no breaking changes in this release.

Known Issues

  • NVSHMEM can only be linked statically.

    This is because the linking of CUDA device symbols does not work across shared libraries.

  • nvshmem_barrier*, nvshmem_quiet, and nvshmem_wait_until only ensure PE-PE ordering and visibility on systems with NVLink and InfiniBand.

    They do not ensure global ordering and visibility.

  • Complex types, which are enabled by setting NVSHMEM_COMPLEX_SUPPORT at compile time, are not currently supported.
  • When built with GDRcopy and when using Infiniband, NVSHMEM cannot allocate the complete device memory because of the inability to reuse the BAR1 space.

    This will be fixed with future CUDA driver releases in the 470 (or later) and in the 460 branch.

  • When NVSHMEM maps the symmetric heap using cudaMalloc, it sets the CU_POINTER_ATTRIBUTE_SYNC_MEMOPS attribute, which automatically synchronizes synchronous CUDA memory operations on the symmetric heap.

    With CUDA 11.3 and later, NVSHMEM supports the mapping of the symmetric heap by using the CUDA VMM APIs. However, when you map the symmetric heap by using the VMM APIs, CUDA does not support this attribute, and users are responsible for synchronization. For additional information about synchronous CUDA memory operations, see API synchronization behavior.