11 #ifndef _QB_SPI_SLAVE_H_
12 #define _QB_SPI_SLAVE_H_
32 #define QB_SPI_SLAVE_ARM 0
34 #define QB_SPI_SLAVE_XFER_COMPLETE 1
36 #define QB_SPI_SLAVE_UNARM 2
38 #define QB_SPI_SLAVE_REG_DUMP 3
40 #define QB_SPI_SLAVE_RESET 4
45 #define QB_PIO_DMA_TRANSFER_LIMIT_RX 32
46 #define QB_PIO_DMA_TRANSFER_LIMIT_TX 8
47 #define MAX_SPI_SLAVE_XFERSIZE 65536
49 #define QB_SPI_SLAVE_MAX_INSTANCES 4
53 #define FLUSH_FIFO_TIMEOUT 1000
175 #endif // _QB_SPI_SLAVE_H_
enum QbSpiSlaveModeRec QbSpiSlaveMode
Defines the SPI modes.
NvU32 RequestLength
Holds the number of bytes requested to be transferred.
NvU32 SlaveArmTimeout
Holds the timeout value in miliseconds for arm operation.
QbSpiSlaveCSPolarity ChipSelectPolarity
Holds the chip select polarity.
QbSpiSlaveCSPolarityRec
Defines the polarity for SPI chip select.
QbSpiSlaveMode Mode
Holds the SPI mode.
QbSpiSlaveInstance Instance
Holds the SPI instance.
enum QbSpiSlaveCSPolarityRec QbSpiSlaveCSPolarity
Defines the polarity for SPI chip select.
struct QbSpiSlaveControllerInfo * DevInfo
Holds SPI slave controller info.
enum QbSpiSlaveChipSelectRec QbSpiSlaveChipSelect
Defines the SPI chip select.
NvU32 GpcDmaClientID
Holds the GPCDMA client ID.
NvU32 SlaveReadyGpioPolarity
Holds the slave-ready GPIO polarity.
NvU8 * pDataRxBuffer
Holds the buffer for Rx transfer.
Holds the SPI controller specific information.
enum QbSpiSlaveInstanceRec QbSpiSlaveInstance
Defines the SPI controller instance.
QbSpiSlaveChipSelectRec
Defines the SPI chip select.
NvU32 DmaChannel
Holds the DMA channel information.
Holds private information for SPI slave driver.
NvU32 XferInProgress
Holds weather a transfer is in progress for this instance.
QbSpiSlaveChipSelect ChipSelect
Holds the chip select.
NvError QbSpiSlaveInit(void)
Registers the SPI slave driver to the driver framework.
Holds data for SPI slave transfers.
NVIDIA Quickboot Interface: Error Handling (Parker)
NvU32 SlaveReadyGpioPin
Holds the slave-ready GPIO pin.
NvU8 * pDataTxBuffer
Holds the buffer for Tx transfer.
NvU32 ResetID
Holds the reset ID.
NvU32 SlaveReadyGpioPort
Holds the slave-ready GPIO port.
QbSpiSlaveModeRec
Defines the SPI modes.
NvU32 RegVirtBase
Holds the virtual address of controller (filled by the driver).
QbSpiSlaveInstanceRec
Defines the SPI controller instance.
NvU32 RegLen
Holds the register length of the controller (filled by the driver).
NvU32 RegPhyBase
Holds the physical address of controller (filled by the driver).