spi_slave.h

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/*
 * Copyright (c) 2015-2016, NVIDIA CORPORATION.  All rights reserved.
 *
 * NVIDIA CORPORATION and its licensors retain all intellectual property
 * and proprietary rights in and to this software, related documentation
 * and any modifications thereto.  Any use, reproduction, disclosure or
 * distribution of this software and related documentation without an express
 * license agreement from NVIDIA CORPORATION is strictly prohibited.
 */

#ifndef _QB_SPI_SLAVE_H_
#define _QB_SPI_SLAVE_H_

#include <nvcommon.h>
#include <nverror.h>

#define QB_SPI_SLAVE_ARM                 0
#define QB_SPI_SLAVE_XFER_COMPLETE       1
#define QB_SPI_SLAVE_UNARM               2
#define QB_SPI_SLAVE_REG_DUMP            3
#define QB_SPI_SLAVE_RESET               4

#define QB_PIO_DMA_TRANSFER_LIMIT_RX    32
#define QB_PIO_DMA_TRANSFER_LIMIT_TX     8
#define MAX_SPI_SLAVE_XFERSIZE       65536
#define QB_SPI_SLAVE_MAX_INSTANCES       4

#define FLUSH_FIFO_TIMEOUT            1000

#define DATA_DIR_TX                      0
#define DATA_DIR_RX                      1

typedef enum QbSpiSlaveInstanceRec
{
    QbSpiSlaveInstance_1 = 0, //SPI1
    QbSpiSlaveInstance_2,     //SPI2
    QbSpiSlaveInstance_3,     //SPI3
    QbSpiSlaveInstance_4,     //SPI4
    QbSpiSlaveInstance_Num,
    QbSpiSlaveInstance_Force32 = 0x7fffffff
} QbSpiSlaveInstance;

typedef enum QbSpiSlaveChipSelectRec
{
    QbSpiSlaveCS_0 = 0,
    QbSpiSlaveCS_1,
    QbSpiSlaveCS_2,
    QbSpiSlaveCS_3,
    QbSpiSlaveCS_Num,
    QbSpiSlaveCS_Force32 = 0x7fffffff
} QbSpiSlaveChipSelect;

typedef enum QbSpiSlaveCSPolarityRec
{
    QbSpiSlaveCSPol_LOW = 0,
    QbSpiSlaveCSPol_HIGH,
    QbSpiSlaveCSPol_Num,
    QbSpiSlaveCSPol_Force32 = 0x7fffffff
} QbSpiSlaveCSPolarity;

typedef enum QbSpiSlaveModeRec
{
    QbSpiSlaveMode_0 = 0,
    QbSpiSlaveMode_1,
    QbSpiSlaveMode_2,
    QbSpiSlaveMode_3,
    QbSpiSlaveMode_Num,
    QbSpiSlaveMode_Force32 = 0x7fffffff
} QbSpiSlaveMode;

struct QbSpiSlaveControllerInfo
{
    QbSpiSlaveInstance Instance;
    QbSpiSlaveChipSelect ChipSelect;
    QbSpiSlaveCSPolarity ChipSelectPolarity;
    QbSpiSlaveMode Mode;
    NvU32 DmaChannel;
    NvU32 SlaveReadyGpioPort;
    NvU32 SlaveReadyGpioPin;
    NvU32 SlaveReadyGpioPolarity;
    NvU32 SlaveArmTimeout;
};

struct QbSpiSlaveDriverPrivInfo
{
    NvU32 RegPhyBase;
    NvU32 RegLen;
    NvU32 RegVirtBase;
    NvU32 GpcDmaClientID;
    NvU32 XferInProgress;
    NvU32 ResetID;
    struct QbSpiSlaveControllerInfo *DevInfo;
};

struct QbSpiSlaveTransfer
{
    NvU8 *pDataRxBuffer;
    NvU8 *pDataTxBuffer;
    NvU32 RequestLength;
};

NvError QbSpiSlaveInit(void);

#endif // _QB_SPI_SLAVE_H_